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independent clock quad hotlink ii? transceive r cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-02065 rev. *e revised july 8, 2005 features ? second-generation hotlink ? technology ? compliant to multiple standards ? escon, dvb-asi, smpt e-292m, smpte-259m, fibre channel and gigabit ethernet (ieee802.3z) ? cpri? compliant ? cyw15g0403dxb compliant to obsai-rp3 ? 8b/10b coded data or 10 bit uncoded data ? quad channel transceiver operates from 195 to 1500 mbaud serial data rate ? cyw15g0403dxb operates from 195 to 1540 mbaud ? aggregate throughput of up to 12 gbits/second ? second-generation hotlink ? technology ? truly independent channels ? each channel can operate at a different signaling rate ? each channel can transport a different type of data ? selectable input/output clocking options ? internal phase-locked loops (plls) with no external pll components ? dual differential pecl-compatible serial inputs per channel ? internal dc-restoration ? dual differential pecl-compatible serial outputs per channel ? source matched for 50 ? transmission lines ? no external bias resistors required ? signaling-rate controlled edge-rates ? multiframe? receive framer provides alignment options ? bit and byte alignment ? comma or full k28.5 detect ? single or multi-byte framer for byte alignment ? low-latency option ? synchronous lvttl parallel interface ? jtag boundary scan ? built-in self-test (bist) for at-speed link testing ? compatible with ? fiber-optic modules ? copper cables ? circuit board traces ? per-channel link quality indicator ? analog signal detect ? digital signal detect ? low-power 3w @ 3.3v typical ? single 3.3v supply ? 256-ball thermally enhanced bga ? pb-free package option available ?0.25 bicmos technology functional description the cyp(v)15g0403dxb [1] independent clock quad hotlink ii? transceiver is a point-to-point or point-to-multi- point communications building block enabling transfer of data over a variety of high-speed serial links like optical fiber, balanced, and unbalanced copper transmission lines. the signaling rate can be anywhere in the range of 195 to 1500 mbaud per serial link. each channel operates independently with its own reference clock allowing different rates. each transmit channel accepts parallel characters in an input register, encodes each character for transport, and then converts it to serial data. each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an output register. figure 1 illustrates typical connections between independent host systems and corresponding cyp(v)(w)15g0403dxb chips. note: 1. CYV15G0403DXB refers to smpte 259m and smpte 292m compliant devices. cyw15g0403dxb refers to obsai rp3 compliant devices (max imum operating data rate is 1540 mbaud). cyp15g0403dxb refers to devices not compliant to smpte 259m and smpte 292m pathological tes t requirements and also obsai rp3 operating datarate of 1536 mbaud. cyp(v)(w)15g0403dxb refers to all three devices. figure 1. hotlink ii? system connections system host serial links 10 10 10 10 10 10 10 10 system host 10 10 10 10 10 10 10 10 serial links serial links serial links backplane or cabled connections independent cyp(v)(w)15g0403dxb cyp(v)(w)15g0403dxb independent
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 2 of 43 the cyw15g0403dxb [1] operates from 195 to 1540 mbaud, which includes operation at th e obsai rp3 datarate of both 1536 mbaud and 768 mbaud. the CYV15G0403DXB satisfies the smpte-259m and smpte-292m compliance as per smpte eg34-1999 patho- logical test requirements. as a second-generation hotlink device, the cyp(v)(w)15g0403dxb extends the hotlink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data, command, and bist) with other hotlink device s. the transmit (tx) section of the cyp(v)(w)15g0403dxb quad hotlink ii consists of four independent byte-wide channels. each channel can accept either 8-bit data charac ters or preencoded 10-bit trans- mission characters. data characters may be passed from the transmit input register to an integrated 8b/10b encoder to improve their serial transmission characteristics. these encoded characters are then se rialized and output from dual positive ecl (pecl) compatible differential transmission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel. the receive (rx) section of the cyp(v)(w)15g0403dxb quad hotlink ii consists of four independent byte-wide channels. each channel accepts a serial bit-stream from one of two pecl-compatible differential line receivers, and using a completely integrated clock and data recovery pll, recovers the timing information necessary for data recon- struction. each recovered bi t-stream is deserialized and framed into characters, 8b/10b decoded, and checked for transmission errors. recovered decoded characters are then written to an internal elasticity buffer, and presented to the destination host system. the integrated 8b/10b encoder/decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface. the parallel i/o interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. in addition to clocking the transmit path with a local reference clock, the receive interface may also be configured to present data relative to a recovered clock or to a local reference clock. each transmit and receive channel contains an independent bist pattern generator and checker. this bist hardware allows at-speed testing of the high-speed serial data paths in each transmit and receive section, and across the intercon- necting links. the cyp(v)(w)15g0403dxb is ideal for port applications where different data rates and serial interface standards are necessary for each channel. some applications include multi- protocol routers, aggregati on equipment, and switches. cyp(v)(w)15g0403dxb transceiver logic block diagram x10 serializer phase encoder 8b/10b decoder 8b/10b x11 framer deserializer tx rx x10 serializer encoder 8b/10b decoder 8b/10b x11 framer deserializer tx rx x10 serializer encoder 8b/10b decoder 8b/10b x11 framer deserializer tx rx x10 serializer encoder 8b/10b decoder 8b/10b x11 framer deserializer tx rx txda[7:0] rxda[7:0] txdb[7:0] rxdb[7:0] txdc[7:0] rxdc[7:0] txdd[7:0] rxdd[7:0] outa1 outa2 ina1 ina2 outb1 outb2 inb1 inb2 outc1 outc2 inc1 inc2 outd1 outd2 ind1 ind2 align buffer phase align buffer phase align buffer phase align buffer elasticity buffer elasticity buffer elasticity buffer elasticity buffer txcta[1:0] rxsta[2:0] txctb[1:0] rxstb[2:0] txctc[1:0] rxstc[2:0] txctd[1:0] rxstd[2:0] refclka refclkb refclkc refclkd
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 3 of 43 shifter txlba txlbc transmit path block diagram txratea input register phase-align buffer encoder bist lfsr spdsela refclka+ refclka? transmit pll clock multiplier txclka bit-rate clock character-rate clock a outa1+ outa1? outa2+ outa2? 8 txrateb input register phase-align buffer encoder bist lfsr shifter spdselb refclkb+ refclkb? bit-rate clock character-rate clock b outb1+ outb1? outb2+ outb2? input register phase-align buffer 8b/10b bist lfsr transmit pll clock multiplier a input register phase-align buffer 8b/10b bist lfsr shifter txclkb txratec input register phase-align buffer 8b/10b bist lfsr spdselc refclkc+ refclkc? txclkc bit-rate clock character-rate clock c txrated input register phase-align buffer 8b/10b bist lfsr shifter spdseld refclkd+ refclkd? transmit pll clock multiplier d txclkd bit-rate clock character-rate clock d outd1+ outd1? outd2+ outd2? outc1+ outc1? outc2+ outc2? txcta[1:0] txdd[7:0] oea[2..1] txbist encbypa txcksela = internal signal txerra txerrb txerrd txerrc txclkoa txclkob txclkoc txclkod txda[7:0] 2 txdb[7:0] 8 2 txctb[1:0] 8 2 txdc[7:0] txctc[1:0] 8 2 txctd[1:0] 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 a encbypb encbypc encbypd txbist b txbist c txbistd oeb[2..1] oec[2..1] oed[2..1] pabrsta pabrstb pabrstc pabrstd oea[2..1] oeb[2..1] oec[2..1] oed[2..1] txlbd shifter txlbb transmit pll clock multiplier b transmit pll clock multiplier c 1 0 txckselb 0 txckselc 1 0 txckseld 1 0 txlb[a..d] are internal serial loopback signals encoder encoder encoder encoder 1
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 4 of 43 ina1+ ina1? ina2+ ina2? insela inb1+ inb1? inb2+ inb2? inselb inc1+ inc1? inc2+ inc2? inselc ind1+ ind1? ind2+ ind2? inseld clock & data recovery pll shifter clock & data recovery pll shifter clock & data recovery pll shifter clock & data recovery pll shifter lfid lfic lfib lfia 8 rxstc[2:0] rxdc[7:0] 3 8 rxstb[2:0] rxdb[7:0] 3 8 rxstd[2:0] rxdd[7:0] 3 8 rxsta[2:0] rxda[7:0] 3 receive signal monitor receive signal monitor receive signal monitor receive signal monitor output register output register output register output register elasticity buffer framer rxclkd+ rxclkd? 10b/8b bist elasticity buffer 10b/8b bist framer elasticity buffer 10b/8b bist framer elasticity buffer 10b/8b bist framer 2 rxclkc+ rxclkc? 2 rxclkb+ rxclkb? 2 rxclka+ rxclka? 2 rxrate[a..d] framchar[a..d] rfen[a..d] sdasela[1:0] jtag boundary scan controller tdo tms tclk tdi clock select clock select clock select clock select rxcksel[a..d] reset receive path block diagram = internal signal rxpllpda rfmode[a..d][1:0] lpena rxbist[a..d] decmode[a..d] lpenb lpenc lpend trst sdaselb[1:0] rxpllpdb sdaselc[1:0] rxpllpdc sdaseld[1:0] rxpllpdd decbyp[a..d] spdsela spdselb spdselc spdseld ulcb ulca ulcc ulcd ldtden txlbd txlbc txlbb txlba txlb[a..d] are internal serial loopback signals
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 5 of 43 pin configuration (top view) wren addr[3:0] data[7:0] device configuration and control block diagram = internal signal rxrate[a..d] framchar[a..d] rfen[a..d] rxcksel[a..d] rfmode[a..d][1:0] rxbist[a..d] decmode[a..d] decbyp[a..d] sdasel[2..1][a..d][1:0] rxpllpd[a..d] txrate[a..d] txcksel[a..d] txbist[a..d] oe[2..1][a..d] pabrst[a..d] encbyp[a..d] glen[11..0] fglen[2..0] device configuration and control interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a in c1? out c1? in c2? out c2? v cc in d1? out d1? gnd in d2? out d2? in a1? out a1? gnd in a2? out a2? v cc in b1? out b1? in b2? out b2? b in c1+ out c1+ in c2+ out c2+ v cc in d1+ out d1+ gnd in d2+ out d2+ in a1+ out a1+ gnd in a2+ out a2+ v cc in b1+ out b1+ in b2+ out b2+ c tdi tms inselc inselb v cc ulcd ulcc gnd data [7] data [5] data [3] data [1] gnd nc spd seld v cc ldtd en trst lpend tdo d tclk reset inseld insela v cc ulca spd selc gnd data [6] data [4] data [2] data [0] gnd lpenb ulcb v cc lpena lten1 scan en2 tmen3 e v cc v cc v cc v cc v cc v cc v cc v cc f rx dc[6] rx dc[7] tx dc[0] nc nc rx stb[1] tx clkob rx stb[0] g tx dc[7] wren tx dc[4] tx dc[1] spd selb lp enc spd sela rx db[1] h gnd gnd gnd gnd gnd gnd gnd gnd j tx ctc[1] tx dc[5] tx dc[2] tx dc[3] rx stb[2] rx db[0] rx db[5] rx db[2] k rx dc[2] ref clkc? tx ctc[0] tx clkc rx db[3] rx db[4] rx db[7] lfib l rx dc[3] ref clkc+ lfic tx dc[6] rx db[6] rx clkb+ rx clkb? tx db[6] m rx dc[4] rx dc[5] nc tx errc ref clkb+ ref clkb? tx errb tx clkb n gnd gnd gnd gnd gnd gnd gnd gnd p rx dc[1] rx dc[0] rx stc[0] rx stc[1] tx db[5] tx db[4] tx db[3] tx db[2] r rx stc[2] tx clkoc rx clkc+ rx clkc? tx db[1] tx db[0] tx ctb[1] tx db[7] t v cc v cc v cc v cc v cc v cc v cc v cc u tx dd[0] tx dd[1] tx dd[2] tx ctd[1] v cc rx dd[2] rx dd[1] gnd tx cta[1] addr [0] ref clkd? tx da[1] gnd tx da[4] tx cta[0] v cc rx da[2] tx ctb[0] rx sta[2] rx sta[1] v tx dd[3] tx dd[4] tx ctd[0] rx dd[6] v cc rx dd[3] rx std[0] gnd rx std[2] addr [2] ref clkd+ tx clkoa gnd tx da[3] tx da[7] v cc rx da[7] rx da[3] rx da[0] rx sta[0] w tx dd[5] tx dd[7] lfid rx clkd? v cc rx dd[4] rx std[1] gnd addr [3] addr [1] rx clka+ tx erra gnd tx da[2] tx da[6] v cc lfia ref clka+ rx da[4] rx da[1] y tx dd[6] tx clkd rx dd[7] rx clkd+ v cc rx dd[5] rx dd[0] gnd tx clkod nc tx clka rx clka? gnd tx da[0] tx da[5] v cc tx errd ref clka? rx da[6] rx da[5]
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 6 of 43 pin configuration (bottom view) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a out b2? in b2? out b1? in b1? v cc out a2? in a2? gnd out a1? in a1? out d2? in d2? gnd out d1? in d1? v cc out c2? in c2? out c1? in c1? b out b2+ in b2+ out b1+ in b1+ v cc out a2+ in a2+ gnd out a1+ in a1+ out d2+ in d2+ gnd out d1+ in d1+ v cc out c2+ in 2+ out c1+ in c1+ c tdo lp end trst ldtd en v cc spd seld nc gnd data [1] data [3] data [5] data [7] gnd ulcc ulcd v cc in selb in selc tms tdi d tmen3 scan en2 lten1 lp ena v cc ulcb lp enb gnd data [0] data [2] data [4] data [6] gnd spd selc ulca v cc in sela in seld reset tclk e v cc v cc v cc v cc v cc v cc v cc v cc f rx stb[0] tx clkob rx stb[1] nc nc tx dc[0] rx dc[7] rx dc[6] g rx db[1] spd sela lp enc spd selb tx dc[1] tx dc[4] wren tx dc[7] h gnd gnd gnd gnd gnd gnd gnd gnd j rx db[2] rx db[5] rx db[0] rx stb[2] tx dc[3] tx dc[2] tx dc[5] tx ctc[1] k lfib rx db[7] rx db[4] rx db[3] tx clkc tx ctc[0] ref clkc? rx dc[2] l tx db[6] rx clkb? rx clkb+ rx db[6] tx dc[6] lfic ref clkc+ rx dc[3] m tx clkb tx errb ref clkb? ref clkb+ tx errc nc rx dc[5] rx dc[4] n gnd gnd gnd gnd gnd gnd gnd gnd p tx db[2] tx db[3] tx db[4] tx db[5] rx stc[1] rx stc[0] rx dc[0] rx dc[1] r tx db[7] tx ctb[1] tx db[0] tx db[1] rx clkc? rx clkc+ tx clkoc rx stc[2] t v cc v cc v cc v cc v cc v cc v cc v cc u rx sta[1] rx sta[2] tx ctb[0] rx da[2] v cc tx cta[0] tx da[4] gnd tx da[1] ref clkd? addr [0] txc ta[1] gnd rx dd[1] rx dd[2] v cc tx ctd[1] tx dd[2] tx dd[1] tx dd[0] v rx sta[0] rx da[0] rx da[3] rx da[7] v cc tx da[7] tx da[3] gnd tx clkoa ref clkd+ addr [2] rx std[2] gnd rx std[0] rx dd[3] v cc rx dd[6] tx ctd[0] tx dd[4] tx dd[3] w rx da[1] rx da[4] ref clka+ lfia v cc tx da[6] tx da[2] gnd tx erra rx clka+ addr [1] addr [3] gnd rx std[1] rx dd[4] v cc rx clkd? lfid tx dd[7] tx dd[5] y rx da[5] rx da[6] ref clka? tx errd v cc tx da[5] tx da[0] gnd rx clka? tx clka nc tx clkod gnd rx dd[0] rx dd[5] v cc rx clkd+ rx dd[7] tx clkd tx dd[6]
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 7 of 43 pin descriptions cyp(v)(w)15g0403dxb quad hotlink ii transceiver name i/o characteristics signal description transmit path data and status signals txda[7:0] txdb[7:0] txdc[7:0] txdd[7:0] lvttl input, synchronous, sampled by the associated txclkx or refclkx [2] transmit data inputs . txdx[7:0] data inputs are captured on the rising edge of the transmit interface clock. the transmit inte rface clock is select ed by the txckselx latch via the device configurat ion interface, and passed to the encoder or transmit shifter. when the encoder is enabled, tx dx[7:0] specifies the specific data or command character sent. txcta[1:0] txctb[1:0] txctc[1:0] txctd[1:0] lvttl input, synchronous, sampled by the associated txclkx or refclkx [2] transmit control . txctx[1:0] inputs are captured on the rising edge of the transmit interface clock. the transmit interface clock is selected by the txckselx latch via the device configuration interf ace, and passed to the encoder or transmit shifter. the txcta[1:0] inputs identify how the associ ated txdx[7:0] characters are interpreted. when the encoder is bypassed, these inputs are interpreted as data bits. when the encoder is enabled, these inputs determine if the txdx[7:0] character is encoded as data, a special character code, or replaced with other special character codes. see table 3 for details. txerra txerrb txerrc txerrd lvttl output, synchronous to refclkx [3] , synchronous to rxclkx when selected as refclkx, asynchronous to transmit channel enable / disable, asynchronous to loss or return of refclkx transmit path error . txerrx is asserted high to indicate detection of a transmit phase-align buffer underflow or overflow. if an underflow or overflow condition is detected, txerrx, for the channel in error, is asserted high and remains asserted until either a word sync sequence is tran smitted on that channel, or the transmit phase-align buffer is re-centered with the pabrstx latch via the device configuration interface. when txbistx = 0, the bist progress is pr esented on the associated txerrx output. the txerrx signal pulses high for one transmit-character clock period to indicate a pass through the bist sequence once every 511 or 527 (depending on rxckselx) character times. if rxckselx = 1, a one character pulse occurs every 527 character times. if rx ckselx = 0, a one character pulse occurs every 511 character times. txerrx is also asserted high, when any of the following conditions is true: ? the txpll for the associated channel is powered down. this occurs when oe2x and oe1x for a given channel are both disabled by setting oe2x = 0 and oe1x = 0. ? the absence of the refclkx signal transmit path clock signals refclka refclkb refclkc refclkd differential lvpecl or single-ended lvttl input clock reference clock . refclkx clock inputs are used as the timing references for the transmit and receive plls. these input clocks may also be selected to clock the transmit and receive parallel interfaces. when driven by a single-ended lvcmos or lvttl clock source, connect the clock source to either the true or complement refclkx input, and leave the alternate re fclkx input open (floating). when driven by an lvpecl clock source, th e clock must be a differenti al clock, using both inputs. txclka txclkb txclkc txclkd lvttl clock input, internal pull-down transmit path input clock . when configuratio n latch txckselx = 0, the associated txclkx input is selected as the charac ter-rate input clock fo r the txdx[7:0] and txctx[1:0] inputs. in this mode, the txclkx input must be frequency-coherent to its associated txclkox output clock, but may be offset in phase by any amount. once initialized, txclkx is allowed to drift in phase as much as 180 degrees. if the input phase of txclkx drifts beyond the handl ing capacity of the phase align buffer, txerrx is asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of the txclkx input clock relative to its associated refclkx is initialized when th e configuration latch pabrstx is written as 0. when the associated txerrx is deasser ted, the phase align buffer is initialized and input characters are correctly captured. notes: 2. when refclkx is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges o f the associated refclkx. 3. when refclkx is configured for half-rate operation, these outputs are presented relative to both the rising and falling edge s of the associated refclkx.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 8 of 43 txclkoa txclkob txclkoc txclkod lvttl output transmit clock output . txclkox output clock is synthesized by each channel?s transmit pll and operates synchronous to the internal transmit character clock. txclkox operates at either the same frequency as refclkx (txratex = 0), or at twice the frequency of refclkx (txrat ex = 1). the transmit clock outputs have no fixed phase relationship to refclkx. receive path data and status signals rxda[7:0] rxdb[7:0] rxdc[7:0] rxdd[7:0] lvttl output, synchronous to the selected rxclk output or refclkx input parallel data output . rxdx[7:0] parallel data outputs change relative to the receive interface clock. the receive interface clock is selected by the rxckselx latch. if rxclkx is a full-rate clock, the rxclkx clock outputs are complementary clocks operating at the character rate. the rxdx[7:0] outputs for the associated receive channels follow rising edge of rxclkx+ or falling edge of rxclkx?. if rxclkx is a half-rate clock, the rxclkx clock outpu ts are complementary clocks operating at half the character rate. the rxdx[7:0] outputs for the associated receive channels follow both the falling and rising edges of the associated rxclkx clock outputs. rxsta[2:0] rxstb[2:0] rxstc[2:0] rxstd[2:0] lvttl output, synchronous to the selected rxclk output or refclkx input parallel status output . rxsta[2:0] status outputs ch ange relative to the receive interface clock. the receive interface clock is selected by the rxckselx latch. if rxclkx is a full-rate clock, the rxclkx clock outputs are complementary clocks operating at the character rate. the rxstax [2:0] outputs for the associated receive channels follow rising edge of rxclkx+ or falling edge of rxclkx?. if rxclkx is a half-rate clock, the rxclkx clock outpu ts are complementary clocks operating at half the character rate. the rxstax[2:0] outputs for the associated receive channels follow both the falling and rising edges of the associated rxclkx clock outputs. when the decoder is bypassed, rxstx[1:0] become the two low-order bits of the 10- bit received character. rxstx[2] = high indicates the presence of a comma character in the output register. when th e decoder is enabled, rxstx[2:0] provide status of the received signal. see table 11 for a list of received character status. receive path clock signals rxclka rxclkb rxclkc rxclkd lvttl output clock receive clock output . rxclkx is the receive interface clock used to control timing of the rxdx[7:0] and rxsta[2:0] parall el outputs. the source of the rxclkx outputs is selected by the rxckselx latc h via the device configuration interface. these true and complement cl ocks are used to control timi ng of data output transfers. these clocks are output continuously at ei ther the dual-character rate (1/20 th the serial bit-rate) or character rate (1/10 th the serial bit-rate) of the data being received, as selected by rxratex. when configured su ch that the output data path is clocked by the refclkx instead of a recovered clock, the rxclkx output drivers present a buffered or divided form (depending on rxratex) of the associated refclkx that are delayed in phase to align with the data. this phase difference allows the user to select the optimal clock (refclkx or rxclk) for setup/hold timing for their specific system. when refclkx is a full-rate clock, the rxclkx rate depends on the value of rxratex. when refclkx is a half-rate clock and rxckselx = 0, the rxclkx rate depends on the value of rxratex. when refclkx is a half-rate clock and rxckselx=1, the rxclkx rate does not depend on the value of rxratex and operates at the same rate as refclkx. device control signals reset lvttl input, asynchronous, internal pull-up asynchronous device reset . reset initializes all state machines, counters, and configuration latches in the device to a known state. reset must be asserted low for a minimum pulse width. when the reset is removed, all state machines, counters and configuration latches are at an initial state. see table 9 for the initialize values of the device configuration latches. pin descriptions (continued) cyp(v)(w)15g0403dxb quad hotlink ii transceiver name i/o characteristics signal description
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 9 of 43 ldtden lvttl input, internal pull-up level detect transition density enable . when ldtden is high, the signal level detector, range controller, and transition density detector are all enabled to determine if the rxpll tracks refclkx or the se lected input serial data stream. if the signal level detector, range controller , or transition density detector are out of their respective limits while ldtden is high, the rxpll locks to refclk until such a time they become valid. the (sdasel[a..d][1:0]) are used to configure the trip level of the signal level detector. the transition density detector limit is one transition in every 60 consecutive bits. when ldtden is low, only the range controller is used to dete rmine if the rxpll tracks refclkx or the selected input serial data stream. for the cases when rxc kselx = 0 (recovered clock), it is recom- mended to set ldtden = high. ulca ulcb ulcc ulcd lvttl input, internal pull-up use local clock . when ulcx is low, the rxpll is forced to lock to refclkx instead of the received serial data stream. while ulcx is low, the lfix for the associated channel is low indicating a link fault. when ulcx is high, the rxpll performs clock and data recovery functions on the input data streams. this func tion is used in applications in which a stable rxclkx is needed. in cases when there is an absence of valid data transitions for a long period of time, or the high-gain differential serial inputs (inx) are left floating, there may be brief frequency excursions of the rxclkx outputs from refclkx. spdsela spdselb spdselc spdseld 3-level select [4] static control input serial rate select . the spdselx inputs specify the operating signaling-rate range of each channel?s transmit and receive pll. low = 195 ? 400 mbaud mid = 400 ? 800 mbaud high = 800 ? 1500 mbaud (800?1540 mbaud for cyw15g0403dxb) insela inselb inselc inseld lvttl input, asynchronous receive input selector . the inselx input determines which external serial bit stream is passed to the receiver?s clock a nd data recovery circ uit. when inselx is high, the primary differential serial data in put, inx1, is sele cted for the associated receive channel. when inselx is low, the secondary differential serial data input, inx2, is selected for the associated receive channel. lpena lpenb lpenc lpend lvttl input, asynchronous, internal pull-down loop-back-enable . the lpenx input enables the internal serial loop-back for the associated channel. when lpenx is high, the transmit serial data from the associated channel is internally routed to the associated receive clock and data recovery (cdr) circuit. all enabled serial drivers on the channel are forced to differ- ential logic-1, and the serial data inputs are ignored. when lpenx is low, the internal serial loop-back function is disabled. lfia lfib lfic lfid lvttl output, asynchronous link fault indication output . lfix is an output status indicator signal. lfix is the logical or of six internal conditions. lfix is asserted low when any of the following conditions is true: ? received serial data rate outside expected range ? analog amplitude below expected levels ? transition density lower than expected ? receive channel disabled ?ulcx is low ? absence of refclkx. device configuration and control bus signals wren lvttl input, asynchronous, internal pull-up control write enable . the wren input writes the values of the data[7:0] bus into the latch specified by the addres s location on the addr[3:0] bus. [5] notes: 4. 3-level select inputs are used for static configuration. these ar e ternary inputs that make use of logic levels of low, mid, and high. the low level is usually implemented by direct connection to v ss (ground). the high level is usually implemented by direct connection to v cc (power). the mid level is usually implemented by not connecting the input (left floating), which allows it to self bias to the proper level. 5. see device configuration and control interface for detailed information on the operation of the configuration interface. pin descriptions (continued) cyp(v)(w)15g0403dxb quad hotlink ii transceiver name i/o characteristics signal description
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 10 of 43 addr[3:0] lvttl input asynchronous, internal pull-up control addressing bus . the addr[3:0] bus is the input address bus used to configure the device. the wren input writes the values of the data[7:0] bus into the latch specified by the address location on the addr[3:0] bus. [5] table 9 lists the configuration latches within the device, and the initialization value of the latches upon the assertion of reset . table 10 shows how the latches are mapped in the device. data[7:0] lvttl input asynchronous, internal pull-up control data bus . the data[7:0] bus is the input data bus used to configure the device. the wren input writes the values of the data[7:0] bus into the latch specified by address location on the addr[3:0] bus. [5 ] table 9 lists the configuration latches within the device, and the initializati on value of the latches upon the assertion of reset . table 10 shows how the latches are mapped in the device. internal device configuration latches rfmode[a..d][1:0] internal latch [6] reframe mode select . framchar[a..d] internal latch [6] framing character select . decmode[a..d] internal latch [6] receiver decoder mode select . decbyp[a..d] internal latch [6] receiver decoder bypass . rxcksel[a..d] internal latch [6] receive clock select . rxrate[a..d] internal latch [6] receive clock rate select . sdasel[a..d][1:0] internal latch [6] signal detect amplitude select . encbyp[a..d] internal latch [6] transmit encoder bypassed . txcksel[a..d] internal latch [6] transmit clock select . txrate[a..d] internal latch [6] transmit pll clock rate select . rfen[a..d] internal latch [6] reframe enable . rxpllpd[a..d] internal latch [6] receive channel power control . rxbist[a..d] internal latch [6] receive bist disabled . txbist[a..d] internal latch [6] transmit bist disabled . oe2[a..d] internal latch [6] differential serial output driver 2 enable . oe1[a..d] internal latch [6] differential serial output driver 1 enable . pabrst[a..d] internal latch [6] transmit clock phase alignment buffer reset . glen[11..0] internal latch [6] global latch enable . fglen[2..0] internal latch [6] force global latch enable . factory test modes lten1 lvttl input, internal pull-down factory test 1 . lten1 input is for factory testing only. this input may be left as a no connect, or gnd only. scanen2 lvttl input, internal pull-down factory test 2. scanen2 input is for factory testing only. this input may be left as a no connect, or gnd only. tmen3 lvttl input, internal pull-down factory test 3 . tmen3 input is for factory testing only. this input may be left as a no connect, or gnd only. note: 6. see device configuration and control interface for detailed information on the internal latches. pin descriptions (continued) cyp(v)(w)15g0403dxb quad hotlink ii transceiver name i/o characteristics signal description
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 11 of 43 cyp(v)(w)15g0403dxb hotlink ii operation the cyp(v)(w)15g0403dxb is a highly configurable, independent clocking, quad-channel transceiver designed to support reliable transfer of larg e quantities of data, using high- speed serial links from multiple sources to multiple destina- tions. this device supports four single-byte channels. cyp(v)(w)15g0403dxb transmit data path input register the bits in the input register for each channel support different assignments, based on if the input data is encoded or unencoded. these assignments are shown in table 1 . when the encoder is enabled, each input register captures eight data bits and two control bits on each input clock cycle. when the encoder is bypassed, the control bits are part of the pre-encoded 10-bit character. when the encoder is enabled, the txctx[1:0] bits are inter- preted along with the associated txdx[7:0] character to generate a specific 10-bit transmission character. phase-align buffer data from each input register is passed to the associated phase-align buffer, when the txdx[7:0] and txctx[1:0] input registers are clocked using txclkx| (txckselx = 0 and txratex = 0). when the txdx[7:0] and txctx[1:0] input registers are clocked using refclkx (txckselx = 1) and refclkx is a full-rate clock, the associated phase alignment buffer in the transmit path is bypassed. these buffers are used to absorb clock phase differences between the txclkx input clock and the internal character clock for that channel. once initialized, txclkx is allowed to drift in phase as much as 180 degrees. if the input phase of txclkx drifts beyond the handling capacity of the phase align buffer, txerrx is analog i/o outa1 outb1 outc1 outd1 cml differential output primary differential serial data output . the outx1 pecl-compatible cml outputs (+3.3v referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be ac-coupled for pecl- compatible connections. outa2 outb2 outc2 outd2 cml differential output secondary differential serial data output . the outx2 pecl-compatible cml outputs (+3.3v referenced) are capable of driving terminated transmission lines or standard fiber- optic transmitter modules, and must be ac -coupled for pecl-compatible connections. ina1 inb1 inc1 ind1 differential input primary differential serial data input . the inx1 input accepts the serial data stream for deserialization and decoding. th e inx1 serial stream is passed to the receive cdr circuit to extract the data content when inselx = high. ina2 inb2 inc2 ind2 differential input secondary differential serial data input . the inx2 input accepts the serial data stream for deserialization and decoding. th e inx2 serial stream is passed to the receiver cdr circuit to extract the data content when inselx = low. jtag interface tms lvttl input, internal pull-up test mode select . used to control access to th e jtag test modes. if maintained high for 5 tclk cycles, the jtag test controller is reset. tclk lvttl input, internal pull-down jtag test clock . tdo 3-state lvttl output test data out . jtag data output buffer. high-z while jtag test mode is not selected. tdi lvttl input, internal pull-up test data in . jtag data input port. trst lvttl input, internal pull-up jtag reset signal . when asserted (low), this input asynchronously resets the jtag test access port controller. power v cc +3.3v power . gnd signal and power ground for all internal circuits . pin descriptions (continued) cyp(v)(w)15g0403dxb quad hotlink ii transceiver name i/o characteristics signal description
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 12 of 43 asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of the txclkx relative to its associated internal character rate clock is initialized when the configuration latch pabrstx is written as 0. when the associated txe rrx is deasserted, the phase align buffer is initialized and input characters are correctly captured. if the phase offset, between the initialized location of the input clock and refclkx|, exceeds the skew handling capabilities of the phase-align buffer, an error is reported on that channel?s txerrx output. this output indicates an error continuously until the phase-align buffer for that channel is reset. while the error remains active, the transmitter for that channel outputs a continuous c0.7 character to indicate to the remote receiver that an error condition is present in the link. each phase-align buffer may be individually reset with minimal disruption of the serial data stream. when a phase- align buffer error is present, the transmission of a word sync sequence re-centers the phase-align buffer and clears the error indication. note . k28.5 characters may be added or removed from the data stream during the phase align buffer reset operation. when used with non-cypress devices that require a complete 16-character word sync sequence for proper receive elasticity buffer operation, it is recommend that the phase alignment buffer reset be followed by a word sync sequence to ensure proper operation. encoder each character received from the input register or phase- align buffer is passed to the encoder logic. this block inter- prets each character and any associated control bits, and outputs a 10-bit transmission character. depending on the operational mode, the generated trans- mission character may be ? the 10-bit pre-encoded character accepted in the input register. ? the 10-bit equivalent of the 8-bit data character accepted in the input register. ? the 10-bit equivalent of the 8-bit special character code accepted in the input register. ? the 10-bit equivalent of the c0.7 violation character if a phase-align buffer overflow or underflow error is present. ? a character that is part of the 511-character bist sequence. ? a k28.5 character generated as an individual character or as part of the 16-character word sync sequence. data encoding raw data, as received directly from the transmit input register, is seldom in a form suitable for transmission across a serial link. the characters must usually be processed or transformed to guarantee ? a minimum transition density (to allow the receive pll to extract a clock from the serial data stream). ? a dc-balance in the signaling (to prevent baseline wander). ? run-length limits in the serial data (to limit the bandwidth requirements of the serial link). ? the remote receiver a way of determining the correct character boundaries (framing). when the encoder is enabled (encbypx = 1), the characters transmitted are converted from data or special character codes to 10-bit transmission characters, using an integrated 8b/10b encoder. when directed to encode the character as a special character code, the encoder uses the special character encoding rules listed in ta ble 16 . when directed to encode the character as a data character, it is encoded using the data character encoding rules in table 15 . the 8b/10b encoder is standards compliant with ansi/ncits asc x3.230-1994 fibre channel, ieee 802.3z gigabit ethernet, the ibm ? escon ? and ficon? channels, etsi dvb-asi, and atm forum standards for data transport. many of the special character codes listed in table 16 may be generated by more than one input character. the cyp(v)(w)15g0403dxb is designed to support two independent (but non-overlapping) special character code tables. this allows the cyp(v)(w)15g0403dxb to operate in mixed environments with other cypress hotlink devices using the enhanced cypress command code set, and the reduced command sets of other non-cypress devices. even when used in an environment th at normally uses non-cypress special character codes, the selective use of cypress command codes can permit operation where running disparity and error handling must be managed. following conversion of each inpu t character from eight bits to a 10-bit transmission character, it is passed to the transmit shifter and is shifted out lsb first, as required by ansi and ieee standards for 8b/10b co ded serial data streams. transmit modes encoder bypass when the encoder is bypassed, the character captured from the txdx[7:0] and txctx[1:0] input register is passed directly to the transmit shifter without modification. with the encoder bypassed, the txctx[1:0] inputs are considered part of the data character and do not perform a control function that would otherwise modify the interpretation of the txdx[7:0] bits. the bit usage and mapping of these control bits when the encoder is bypassed is shown in table 2 . note: 7. lsb shifted out first. table 1. input register bit assignments [7] signal name unencoded encoded txdx[0] (lsb) dinx[0] txdx[0] txdx[1] dinx[1] txdx[1] txdx[2] dinx[2] txdx[2] txdx[3] dinx[3] txdx[3] txdx[4] dinx[4] txdx[4] txdx[5] dinx[5] txdx[5] txdx[6] dinx[6] txdx[6] txdx[7] dinx[7] txdx[7] txctx[0] dinx[8] txctx[0] txctx[1] (msb) dinx[9] txctx[1]
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 13 of 43 when the encoder is enabled, the txctx[1:0] data control bits control the interpretation of the txdx[7:0] bits and the characters generated by them. these bits are interpreted as listed in ta ble 3 . word sync sequence when txctx[1:0] = 11, a 16-c haracter sequence of k28.5 characters, known as a word sy nc sequence, is generated on the associated channel. this sequence of k28.5 characters may start with either a positive or negative disparity k28.5 (as determined by the current running disparity and the 8b/10b coding rules). the disparity of the second and third k28.5 characters in this sequence are reversed from what normal 8b/10b coding rules would generate. the remaining k28.5 characters in the sequence follow all 8b/10b coding rules. the disparity of the generated k28.5 characters in this sequence follow a pattern of either ++??+?+?+?+?+?+? or ??++?+?+?+?+?+?+. the generation of this sequenc e, once started, cannot be stopped until all 16 characters have been sent. the content of the associated input registers are ignored for the duration of this sequence. at the end of th is sequence, if the txctx[1:0] = 11 condition is sampled again, the sequence restarts and remains uninterruptible for the following 15 character clocks. transmit bist each transmit channel contains an internal pattern generator that can be used to validate both the link and device operation. these generators are enabled by the associated txbistx latch via the device configuration interface. when enabled, a register in the associated transmit channel becomes a signature pattern generator by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511- character (or 526-character) sequence that includes all data and special character codes, including the explicit violation symbols. this provides a predictable yet pseudo-random sequence that can be matched to an identical lfsr in the attached receiver(s). a device reset (reset sampled low) presets the bist enable latches to disable bist on all channels. all data and data-control information present at the associated txdx[7:0] and txctx[1:0] inputs are ignored when bist is active on that channel. if the receive channels are configured for reference clock operation, each pass is preceded by a 16- character word sync sequence to allow elasticity buffer alignment and management of clock-frequency variations. transmit pll clock multiplier each transmit pll clock multip lier accepts a character-rate or half-character-rate external clock at the associated refclkx input, and that clock is multiplied by 10 or 20 (as selected by txratex) to generate a bit-rate clock for use by the transmit shifter. it also provides a character-rate clock used by the transmit paths, and outputs this character rate clock as txclkox. each clock multiplier pll can accept a refclkx input between 19.5 mhz and 150 mhz (19.5 mhz and 154 mhz for cyw15g0403dxb), however, this clock range is limited by the operating mode of the cyp(v)(w)15g0403dxb clock multiplier (txratex) and by the level on the associated spdselx input. spdselx are 3-level select [4] inputs that select one of three operating ranges for the serial data outputs and inputs of the associated channel. the operating serial signaling-rate and allowable range of refclkx frequencies are listed in table 4 . the refclkx inputs are differential inputs with each input internally biased to 1.4v. if the refclkx+ input is connected to a ttl, lvttl, or lvcmos clock source, the input signal is recognized when it passes through the internally biased reference point. when driven by a single-ended ttl, lvttl, or lvcmos clock source, connect the clock source to either the true or complement refclkx input, and leave the alternate refclkx input open (floating). when both the refclkx+ and refclkx? inputs are connected, the clock source must be a differential clock. this can either be a differ ential lvpecl clock that is dc-or ac- coupled or a differential lvttl or lvcmos clock. by connecting the refclkx? input to an external voltage source, it is possible to adjust the reference point of the refclkx+ input for alternate logic levels. when doing so it is necessary to ensure that the input differential crossing point remains within the parametric range supported by the input. table 2. encoder bypass mode signal name bus weight 10b name txdx[0] (lsb) 2 0 a [7] txdx[1] 2 1 b txdx[2] 2 2 c txdx[3] 2 3 d txdx[4] 2 4 e txdx[5] 2 5 i txdx[6] 2 6 f txdx[7] 2 7 g txctx[0] 2 8 h txctx[1] (msb) 2 9 j table 3. transmit modes txctx[1] txctx[0] characters generated 0 0 encoded data character 0 1 k28.5 fill character 1 0 special character code 1 1 16-character word sync sequence table 4. operating speed settings spdselx txrate refclkx frequency (mhz) signaling rate (mbaud) low 1 reserved 195?400 0 19.5?40 mid (open) 1 20?40 400?800 0 40?80 high 1 40?75 800?1500 (800?1540 for cyw15g0403dxb) 0 80?150
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 14 of 43 serial output drivers the serial output interface dr ivers use differential current mode logic (cml) drivers to provide source-matched drivers for transmission lines. these drivers accept data from the transmit shifters. these drivers have signal swings equivalent to that of standard pecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. when configured for local loopback (lpenx = high), all enabled serial drivers are configured to drive a static differential logic 1. to achieve obsai rp3 complianc y, the serial output drivers must be ac-coupled to the transmission medium. transmit channels enabled each driver can be enabled or disabled separately via the device configuration interface. when a driver is disabled via t he configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. note . when a disabled transmit channel (i.e., both outputs disabled) is re-enabled: ? data on the serial outputs may not meet all timing specifi- cations for up to 250 s ? the state of the phase-align buffer cannot be guaranteed, and a phase-align reset is required if the phase-align buffer is used cyp(v)(w)15g0403dxb receive data path serial line receivers two differential line receivers, inx1 and inx2, are available on each channel for accepting serial data streams. the active serial line receiver on a channel is selected using the associated inselx input. the serial line receiver inputs are differential, and can accommodate wire interconnect and filtering losses or transmissi on line attenuation greater than 16 db. for normal operation, these inputs should receive a signal of at least vi diff > 100 mv, or 200 mv peak-to-peak differential. each line receiver can be dc- or ac-coupled to +3.3v powered fiber-optic interface modules (any ecl/pecl family, not limited to 100k pecl) or ac-coupled to +5v powered optical modules. the common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. each receiver provides internal dc- restoration, to the center of the receiver?s common mode range, for ac-coupled signals. the local internal loopback (lpenx) allows the serial transmit data outputs to be routed internally back to the clock and data recovery circuit associat ed with each channel. when configured for local loopback, the associated transmit serial driver outputs are forced to output a differential logic-1. this prevents local diagnostic patterns from being broadcast to attached remote receivers. signal detect/link fault each selected line receiver (i.e., that routed to the clock and data recovery pll) is simultaneously monitored for ? analog amplitude above amplitude level selected by sdaselx ? transition density above the specified limit ? range controls report the received data stream inside normal frequency range (1500 ppm [30] ) ? receive channel enabled ? presence of reference clock ?ulcx is not asserted. all of these conditions must be valid for the signal detect block to indicate a valid signal is present. this status is presented on the lfix (link fault indicator) output associated with each receive channel, which changes synchronous to the selected receive interface clock. analog amplitude while most signal monitors are based on fixed constants, the analog amplitude level detection is adjustable to allow operation with highly attenuated signals, or in high-noise environments. the analog amplitude level detection is set by the sdaselx latch via device configuration interface. the sdaselx latch sets the trip point for the detection of a valid signal at one of three levels, as listed in table 5 . this control input affects the analog monitors for all receive channels. the analog signal detect monitors are active for the line receiver as selected by the associated inselx input. when configured for local loopback, no input receivers are selected, and the lfix output for each channel reports only the receive vco frequency out-of-range and transition density status of the associated transmit signal. when local loopback is active, the associated analog signal detect monitor is disabled. transition density the transition detection logi c checks for the absence of transitions spanning greater than six transmission characters (60 bits). if no transitions are present in the data received, the detection logic for that channel asserts lfix . range controls the cdr circuit includes logic to monitor the frequency of the pll voltage controlled oscillator (vco) used to sample the incoming data stream. this logic ensures that the vco operates at, or near the rate of the incoming data stream for two primary cases: ? when the incoming data stream resumes after a time in which it has been ?missing.? ? when the incoming data stream is outside the acceptable signaling rate range. to perform this function, the frequency of the rxpll vco is periodically compared to the frequency of the refclkx table 5. analog amplitude detect valid signal levels [8] sdasel typical signal with peak amplitudes above 00 analog signal detector is disabled 01 140 mv p-p differential 10 280 mv p-p differential 11 420 mv p-p differential note: 8. the peak amplitudes listed in this table are for typical wa veforms that have generally 3?4 trans itions for every ten bits. in a worse case environment the signals may have a sine-wave appearance (highest transition density with repeating 0101...). signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mv.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 15 of 43 input. if the vco is running at a frequency beyond 1500 ppm [30] as defined by the refclkx frequency, it is periodically forced to the correct frequency (as defined by refclkx, spdselx, and txratex) and then released in an attempt to lock to the input data stream. the sampling and relock period of the range control is calcu- lated as follows: range_control_ sampling_period = (recovered byte cl ock period) * (4096). during the time that the range control forces the rxpll vco to track refclkx, the lfix output is asserted low. after a valid serial data stream is applied, it may take up to one range control sampling period before the pll locks to the input data stream, after which lfix should be high. receive channel enabled the cyp(v)(w)15g0403dxb contai ns four receive channels that can be independently enabled and disabled. each channel can be enabled or disabled separately through the rxpllpdx input latch as controlled by the device configu- ration interface. when the rxpllpdx latch = 0, the associated pll and analog circuitry of the channel is disabled. any disabled channel indicates a constant link fault condition on the lfix output. when rxpllpdx = 1, the associated pll and receive channel is enabled to receive and decode a serial stream. note . when a disabled receive channel is reenabled, the status of the associated lfix output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms. clock/data recovery the extraction of a bit-rate clock and recovery of bits from each received serial stream is performed by a separate cdr block within each receive channel. the clock extraction function is performed by an integrated pll that tracks the frequency of the transitions in the incoming bit stream and align the phase of the internal bit-rate clock to the transitions in the selected serial data stream. each cdr accepts a character-rate (bit-rate 10) or half- character-rate (bit-rate 20) reference clock from the associated refclkx input. this refclkx input is used to ? ensure that the vco (within the cdr) is operating at the correct frequency (rather than a harmonic of the bit-rate) ? reduce pll acquisition time ? limit unlocked frequency excursions of the cdr vco when there is no input data present at the selected serial line receiver. regardless of the type of signa l present, the cdr attempts to recover a data stream from it. if the signalling rate of the recovered data stream is outside the limits set by the range control monitors, the cdr tra cks refclkx instead of the data stream. once the cdr output (rxclk) frequency returns back close to refclkx frequency, the cdr input is switched back to the input data stream. if no data is present at the selected line receiver, this switching behavior may result in brief rxclk frequency excursions from refclkx. however, the validity of the in put data stream is indicated by the lfix output. the frequency of refclkx is required to be within 1500 ppm [30] of the frequency of the clock that drives the refclkx input of the remote transmitter to ensure a lock to the incoming data stream. for systems using multiple or redundant connections, the lfix output can be used to select an alternate data stream. when an lfix indication is detected, external logic can toggle selection of the associated inx1 and inx2 input through the associated inselx input. when a port switch takes place, it is necessary for the receive pll for that channel to reacquire the new serial stream and frame to the incoming character bound- aries. deserializer/framer each cdr circuit extracts bits from the associated serial data stream and clocks these bits into the shifter/framer at the bit- clock rate. when enabled, the framer examines the data stream looking for one or more comma or k28.5 characters at all possible bit positions. the location of this character in the data stream is used to determi ne the character boundaries of all following characters. framing character the cyp(v)(w)15g0403dxb allows selection of different framing characters on each channel. two combinations of framing characters are support ed to meet the requirements of different interfaces. the selection of the framing character is made through the framcharx latches via the configuration interface. the specific bit combinations of these framing characters are listed in table 6 . when the specific bit combination of the selected framing character is detected by the framer, the boundaries of the characters present in the received data stream are known. framer the framer on each channel operates in one of three different modes. each framer may be enabled or disabled using the rfenx latches via the configuration interface. when the framer is disabled (rfenx = 0), no combination of received bits alters the frame information. when the low-latency framer is selected (rfmodex[1:0] = 00), the framer operates by stretching the recovered character clock until it aligns with the received character boundaries. in this mode the framer starts its alignment process on the first detection of the selected framing character. to reduce the impact on external circuits that use the recovered clock, the clock period is not stretched by more than two bit-periods in any one clock cycle. when operated with a character-rate output clock, the output of pr operly framed characters may be delayed by up to nine char acter-clock cycles from the detection of the selected fram ing character. when operated table 6. framing character selector framcharx bits detected in framer character name bits detected 0 comma+ comma? 00111110xx [9] or 11000001xx 1?k28.5 +k28.5 0011111 010 or 1100000101 note: 9. the standard definition of a comma contains only seven bits. ho wever, since all valid comma characters within the 8b/10b char acter set also have the eighth bit as an inversion of the seventh bit, the compare pattern is ex tended to a full eight bits to reduce the possibility of a fra ming error.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 16 of 43 with a half-character-rate output clock, the output of properly framed characters may be delayed by up to 14 character-clock cycles from the detection of the framing character. note . when receive bist is enabled on a channel, the low- latency framer must not be enabled. the bist sequence contains an aliased k28.5 framing character, which causes the receiver to update its character boundaries incorrectly. when rfmodex[1:0] = 10, the cypress-mode multi-byte framer is selected. the required detection of multiple framing characters makes the associated link much more robust to incorrect framing due to aliased sync characters in the data stream. in this mode, the framer does not adjust the character clock boundary, but instead aligns the character to the already recovered character clock. this ensures that the recovered clock does not contain any significant phase changes or hops during normal operation or framing, and allows the recovered clock to be replicated and distributed to other external circuits or components using pll-based clock distribution elements. in this framing mode the character boundaries are only adjusted if the selected framing character is detected at least twice within a span of 50 bits, with both instances on identical 10-bit character boundaries. when rfmodex[1:0] = 01, th e alternate-mode multi-byte framer is enabled. like the cypress-mode multi-byte framer, multiple framing characters must be detected before the character boundary is adjusted. in this mode, the data stream must contain a minimum of f our of the selected framing characters, received as consec utive characters, on identical 10-bit boundaries, before character framing is adjusted. 10b/8b decoder block the decoder logic block performs two primary functions: ? decoding the received transmission characters to data and special character codes ? comparing generated bist patterns with received characters to permit at-speed link and device testing. the framed parallel output of each deserializer shifter is passed to its associated 10b/8b decoder where, if the decoder is enabled, the input data is transformed from a 10-bit transmission character back to the original data or special character code. this block uses the 10b/8b decoder patterns in table 15 and table 16. received special code characters are decoded using ta ble 16 . valid data characters are indicated by a 000b bit-combination on the associated rxstx[2:0] status bits, and special character codes are indicated by a 001b bit-combination of these status outputs. framing characters, invalid patterns, disparity errors, and synchronization status are presented as alternate combina- tions of these status bits. when decbypx = 0, the 10b/8b decoder is bypassed via the configuration interface. when bypassed, raw 10-bit characters are passed through the receiver and presented at the rxdx[7:0] and the rxsta[1: 0] outputs as 10-bit wide characters. when the decoder is enabled by setting decbypx = 1 via the configuration interface, the 10- bit transmission characters are decoded using table 15 and table 16 . received special characters are decoded using ta ble 16 . the columns used in table 16 are determined by the decmodex latch via the device configuration interface. when decmodex = 0 the alternate table is used and when decmodex = 1 the cypress table is used. receive bist operation the receiver channel contains an internal pattern checker that can be used to validate both device and link operation. these pattern checkers are enabled by the associated rxbistx latch via the device configuration interface. when enabled, a register in the associated receive channel becomes a signature pattern generator and checker by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511-character or 526-character sequence that includes all data and special character codes, including the explicit violation symbols. this provides a predictable yet pseudo-random sequence that can be matched to an identical lfsr in the attached transmit ter(s). when synchronized with the received data stream, th e associated receiver checks each character in the decode r with each character generated by the lfsr and indicates compare errors and bist status at the rxstx[2:0] bits of the output register. when bist is first recognized as being enabled in the receiver, the lfsr is preset to the bist-loop start-code of d0.0. this code d0.0 is sent only once per bist loop. the status of the bist progress and any character mismatches are presented on the rxstx[2:0] status outputs. code rule violations or running disparity errors that occur as part of the bist loop do not cause an error indication. rxstx[2:0] indicates 010b or 100b for one character period per bist loop to indicate loop completion. this status can be used to check test pattern prog ress. these same status values are presented when the decoder is bypassed and bist is enabled on a receive channel. the specific status reported by the bist state machine are listed in table 11 . these same codes are reported on the receive status outputs. the specific patterns checked by each receiver are described in detail in the cypress application note ?hotlink built-in self- test.? the sequence compared by the cyp(v)(w)15g0403dxb is identical to that in the cy7b933, cy7c924dx, and cyp(v)(w)15g0401dxb, allowing interop- erable systems to be built when used at compatible serial signaling rates. if the number of invalid characters received ever exceeds the number of valid characters by 16, the receive bist state machine aborts the compare operations and resets the lfsr to the d0.0 state to look for the start of the bist sequence again. when the receive paths are configured for refclkx operation, each pass must be preceded by a 16-character word sync sequence to allow management of clock frequency variations. the receive bist state machine requires the characters to be correctly framed for it to detect the bist sequence. if the low latency framer is enabled, the framer misaligns to an aliased sync character within the bist sequence. if the alternate multi-byte framer is enabled and the receiver outputs are clocked relative to a recovered clock, it is generally necessary to frame the receiver before bi st is enabled. if the receive outputs are clocked relative to refclkx, the transmitter precedes every 511 character bist sequence with a 16 character-character word sync sequence. a device reset (reset sampled low) presets the bist enable latches to disable bist on all channels.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 17 of 43 receive elasticity buffer each receive channel contains an elasticity buffer that is designed to support multiple clocking modes. these buffers allow data to be read using a clock that is asynchronous in both frequency and phase from the elas ticity buffer write clock, or to be read using a clock that is frequency coherent but with uncontrolled phase relative to the elasticity buffer write clock. if the chip is configured for operation with a recovered clock, the elasticity buffer is bypassed. each elasticity buffer is 10 characters deep, and supports and an 11 bit wide data path. it is capable of supporting a decoded character and three status bits for each character present in the buffer. the write clock for these buffers is always the recovered clock for the associated read channel. receive modes when the receive channel is clocked by refclkx, the rxclkx outputs present a buffered or divided (depending on rxratex) and delayed form of refclkx. in this mode, the receive elasticity buffers are enabled. for refclkx clocking, the elasticity buffers must be able to insert k28.5 characters and delete framing characters as appropriate. the insertion of a k28.5 or delet ion of a framing character can occur at any time on any channel, however, the actual timing of these insertions and deletions is controlled in part by how the transmitter sends its data. in sertion of a k28.5 character can only occur when the receiver has a framing character in the elasticity buffer. likewise, to delete a framing character, one must also be in the elasticity buffer. to prevent a buffer overflow or underflow on a receive channel, a minimum density of framing characters must be present in the received data streams. when the receive channel output register is clocked by a recovered clock, no characters are added or deleted and the receiver elasticity buffer is bypassed. power control the cyp(v)(w)15g0403dxb supports user control of the powered up or down state of each transmit and receive channel. the receive channels are controlled by the rxpllpdx latch via the device configuration interface. when rxpllpdx = 0, the associated pll and analog circuitry of the channel is disabled. the transmit channels are controlled by the oe1x and the oe2x latches via the device configuration interface. when a driver is di sabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. device reset state when the cyp(v)(w)15g0403dxb is reset by assertion of reset , all state machines, counters, and configuration latches in the device are initialized to a reset state, and the elasticity buffer pointers are set to a nominal offset. see table 9 for the initialize values of the configuration latches. following a device reset, it is necessary to enable the transmit and receive channels used for normal operation. this can be done by sequencing the appropriate values on the device configuration interface. [5] output bus each receive channel presents an 11-signal output bus consisting of ? an 8-bit data bus ? a 3-bit status bus. the signals present on this output bus are modified by the present operating mode of the cyp(v)(w)15g0403dxb as selected by the dec bypx configuration latch. this mapping is shown in table 7 . when the 10b/8b decoder is bypassed, the framed 10-bit value is presented to the as sociated output register, along with a status output signal indicating if the character in the output register is one of the selected framing characters. the bit usage and mapping of the ex ternal signals to the raw 10b transmission character is shown in table 8 . the comdetx status output operates the same regardless of the bit combination selected for character framing by the framcharx latch. comdetx is high when the character in the output register contains t he selected framing character at the proper character boundary, and low for all other bit combinations. table 7. output register bit assignments signal name bypass active (decbypx = 0) decoder (decbyp = 1) rxstx[2] (lsb) comdetx rxstx[2] rxstx[1] doutx[0] rxstx[1] rxstx[0] doutx[1] rxstx[0] rxdx[0] doutx[2] rxdx[0] rxdx[1] doutx[3] rxdx[1] rxdx[2] doutx[4] rxdx[2] rxdx[3] doutx[5] rxdx[3] rxdx[4] doutx[6] rxdx[4] rxdx[5] doutx[7] rxdx[5] rxdx[6] doutx[8] rxdx[6] rxdx[7] (msb) doutx[9] rxdx[7] table 8. decoder bypass mode signal name bus weight 10 bit name rxstx[2] (lsb) comdetx rxstx[1] 2 0 a rxstx[0] 2 1 b rxdx[0] 2 2 c rxdx[1] 2 3 d rxdx[2] 2 4 e rxdx[3] 2 5 i rxdx[4] 2 6 f rxdx[5] 2 7 g rxdx[6] 2 8 h rxdx[7] (msb) 2 9 j
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 18 of 43 when the low-latency framer and half-rate receive port clocking are also enabled, the framer stretches the recovered clock to the nearest 20-bit bou ndary such that the rising edge of rxclkx+ occurs when comdetx is present on the associated output bus. when the cypress or alternate mode framer is enabled and half-rate receive port clocking is also enabled, the output clock is not modified when framing is detected, but a single pipeline stage may be added or subtracted from the data stream by the framer logic such that the rising edge of rxclkx+ occurs when comdetx is present on th e associated output bus. this adjustment only occurs when the framer is enabled. when the framer is disabled, the clock boundaries are not adjusted, and comdetx may be asserted during the rising edge of rxclkx? (if an odd nu mber of characters were received following the initial framing). receive status bits when the 10b/8b decoder is enabled, each character presented at the output regist er includes three associated status bits. these bits are used to identify ? if the contents of the data bus are valid, ? the type of character present, ? the state of receive bist operations, ? character violations. these conditions often overlap; e.g. a valid data character received with incorrect running disparity is not reported as a valid data character. it is instead reported as a decoder violation of some specific type. this implies a hierarchy or priority level to the various status bit combinations. the hierarchy and value of each status are listed in table 11 . a second status mapping, listed in table 11 , is used when the receive channel is configured for bist operation. this status is used to report receive bist status and progress. bist status state machine when a receive path is enabled to look for and compare the received data stream with the bi st pattern, the rxstx[2:0] bits identify the present state of the bist compare operation. the bist state machine has multiple states, as shown in figure 2 and table 11 . when the receive pll detects an out- of-lock condition, the bist stat e is forced to the start-of-bist state, regardless of the pres ent state of the bist state machine. if the number of detected errors ever exceeds the number of valid matches by greater than 16, the state machine is forced to the wait_for_bist state where it monitors the receive path for the first character of the next bist sequence (d0.0). also, if the elasticity buffer ever hits an overflow/underflow condition, the status is forced to the bist_start until the buffer is re-centered (approximately nine character periods). to ensure compatibility between the source and destination systems when operating in bist modes, the sending and receiving ends of the link must use the same receive clock configuration. device configuration and control interface the cyp(v)(w)15g0403dxb is highly configurable via the configuration interface. the conf iguration interface allows the device to be configured globally or allows each channel to be configured independently. table 9 lists the configuration latches within the device including the initialization value of the latches upon the assertion of reset . table 10 shows how the latches are mapped in the device. each row in the ta ble 10 maps to a 8-bit latch bank. ther e are 16 such write-only latch banks. when wren = 0, the logic value in the data[7:0] is latched to the latch bank specifie d by the values in addr[3:0]. the second column of table 10 specifies the channels associated with the corresponding latch bank. for example, the first three latch banks (0,1 and 2) consist of configuration bits for channel a. the latch banks 12, 13 and 14 consist of global configuration bits and the last latch bank (15) is the mask latch bank that can be co nfigured to perform bit-by-bit configuration. global enable function the global enable function, cont rolled by the glenx bits, is a feature that can be used to reduce the number of write opera- tions needed to setup the latch banks. this function is beneficial in system s that use a common configuration in multiple channels. the glenx bit is present in bit 0 of latch banks 0 through 11 only. its default value (1) enables the global update of the latch bank's contents. setting the glenx bit to 0 disables this functionality. latch banks 12, 13, and 14 are used to load values in the related latch banks in a global manner. a write operation to latch bank 12 could do a global write to latch banks 0, 3, 6, and 9 depending on the value of glenx in these latch banks; latch bank 13 could do a global write to latch banks 1, 4, 7 and 10; and latch banks 14 could do a global write to latch banks 2, 5, 8 and 11. the glenx bit cannot be modified by a global write operation. force global enable function fglenx forces the global update of the target latch banks, but does not change the contents of the glenx bits. if fglenx = 1 for the associated global channel, fglenx forces the global update of the target latch banks. mask function an additional latch bank (15) is used as a global mask vector to control the update of the c onfiguration latch banks on a bit- by-bit basis. a logic 1 in a bit location allows for the update of that same location of the target latch bank(s), whereas a logic 0 disables it. the reset value of this latch bank is ffh, thereby making its use optional by default. the mask latch bank is not maskable. the fglen functionality is not affected by the bit 0 value of the mask latch bank. latch types there are two types of latch banks: static (s) and dynamic (d). each channel is configured by 2 static and 1 dynamic latch banks. the s type contain those settings that normally do not change for a given application, whereas the d type controls the settings that could change dynamically during the appli- cation's lifetime.the first row of latches for each channel (address numbers 0, 3, 7, and 10) are the static receiver control latches. the second row of latches for each channel (address numbers 1, 4, 8, and 11) are the static transmitter control latches. the third row of latches for each channel (address numbers 2, 5, 9, and 12) are the dynamic control latches that are associated wit h enabling dynamic functions within the device.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 19 of 43 latch bank 14 is also useful for those users that do not need the latch-based programmable feature of the device. this latch bank could be used in thos e applications that do not need to modify the default value of the static latch banks, and that can afford a global (i.e., not independent) control of the dynamic signals. in this case, this feature becomes available when addr[3:0] is left unchange d with a value of ?1110? and wren is left asserted. the signals present in data[7:0] effec- tively become global control pins, and for the latch banks 2, 5, 8 and 11. table 9. device configuration and control latch descriptions name signal description rfmodea[1:0] rfmodeb[1:0] rfmodec[1:0] rfmoded[1:0] reframe mode select . the initialization value of the rfmodex [1:0] latches = 10. rfmodex is used to select the operating mode of the framer. when rfmodex[1:0] = 00, the lo w-latency framer is selected. this frames on each occurrence of the selected framing charac ter(s) in the received data stream. this mode of framing stretches the recovered clock for one or multiple cycles to align that clock with the recovered data. when rfmodex[1:0] = 01, the alternate mode multi-byte parallel framer is selected. this requires detection of the selected framing character(s) in the received serial bit stream, on identical 10-bit boundaries, on four directly adjacent characters. the recovered characte r clock remains in the same phasing regardless of character offset. when rfmodex[1:0] =10, the cypress-mode multi-byte parallel framer is selected. this requires a pair of the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits, before the character boundaries are adjusted. the recovered character clock remains in the same phasing regardless of character offset. rfmodex[1:0] = 11 is reserved for test. framchara framcharb framcharc framchard framing character select . the initialization value of the framch arx latch = 1. fram charx is used to select the character or portion of a character used fo r framing of each channel?s received data stream. when framcharx = 1, the framer looks for either disparit y of the k28.5 character. when framcharx = 0, the framer looks for either disparity of the 8-bit comma char acters. the specific bit comb inations of these framing characters are listed in table 6 . decmodea decmodeb decmodec decmoded receiver decoder mode select . the initialization value of the decm odex latch = 1. decmodex selects the decoder mode used for the associated channel . when decmodex = 1 and decoder is enabled, the cypress decoding mode is used. when decmodex = 0 and decoder is enabled, the alternate decoding mode is used. when the decoder is enabled (decbypx = 1), the 10-bit transmission characters are decoded using table 15 and table 16 . the column used in the special characters table 16 is determined by the decmodex latch. decbypa decbypb decbypc decbypd receiver decoder bypass . the initialization value of the decbypx latch = 1. decbypx selects if the receiver decoder is enabled or bypassed. when de cbypx = 1, the decoder is enabled and the decoder mode is selected by decmodex. when decbypx = 0, the decoder is bypassed and raw 10-bit characters are passed through the receiver. rxcksela rxckselb rxckselc rxckseld receive clock select . the initializati on value of the rxckselx latch = 1. rxckselx selects the receive clock source used to transfer data to the output registers and the clock source for the rxclk output. when rxckselx = 1, the associated output registers , are clocked by refclkx at the associated rxclkx output buffer. when rxckselx = 0, t he associated output registers, are clocked by the recovered byte clock at the associated rxclkx output buffer. these output clocks may operate at the character-rate or half the character-rate as selected by rxratex. rxratea rxrateb rxratec rxrated receive clock rate select . the initialization value of the rxratex latch = 1. rxratex is used to select the rate of the rxclkx clock output. when rxratex = 1 and rxckselx = 0, the rxclkx cl ock outputs are complement ary clocks that follow the recovered clock operating at half the character ra te. data for the associated receive channels should be latched alternately on the rising edge of rxclkx+ and rxclkx?. when rxratex = 0 and rxckselx = 0, the rxclkx cl ock outputs are complement ary clocks that follow the recovered clock operating at the character rate. data for the associated receive channels should be latched on the rising edge of rxclkx+ or falling edge of rxclkx?. when rxratex = 1 with rxckselx = 1 and refclkx is a full-rate clock, the rxclkx clock outputs are complementary clocks that follow th e reference clock operati ng at half the characte r rate. data for the associated receive channels should be latched alternat ely on the rising edge of rxclkx+ and rxclkx?. when rxratex = 0 with rxckselx = 1 and refclkx is a full-rate clock, the rxclkx clock outputs are complementary clocks that follow the reference clock ope rating at the character rate . data for the associated receive channels should be latched on the rising edge of rxclkx+ or falling edge of rxclkx?. when rxckselx = 1 and refclkx is a half-rate clock, the value of rxratex is not interpreted and the rxclkx clock outputs are complementary clocks that follow the reference cl ock operating at half the character rate. data for the associated receive channel s should be latched alternately on the rising edge of rxclkx+ and rxclkx?.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 20 of 43 sdasel1a[1:0] sdasel1b[1:0] sdasel1c[1:0] sdasel1d[1:0] primary serial data input signal detector amplitude select . the initialization value of the sdasel1x[1:0] latch = 10. sdasel1x[1:0] sele cts the trip point for the detection of a valid signal for the inx1 primary differential serial data inputs. when sdasel1x[1:0] = 00, the analog signal detector is disabled. when sdasel1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mv. when sdasel1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mv. when sdasel1x[1:0] = 11, the ty pical p-p differenti al voltage threshol d level is 420 mv. sdasel2a[1:0] sdasel2b[1:0] sdasel2c[1:0] sdasel2d[1:0] secondary serial data input signal detector amplitude select . the initialization value of the sdasel2x[1:0] latch = 10. sdasel2x[1:0] selects the trip point for the detection of a valid signal for the inx2 secondary differential serial data inputs. when sdasel2x[1:0] = 00, the analog signal detector is disabled when sdasel2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mv. when sdasel2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mv. when sdasel2x[1:0] = 11, the ty pical p-p differenti al voltage threshol d level is 420 mv. encbypa encbypb encbypc encbypd transmit encoder bypassed . the initialization value of the encbypx latch = 1. encbypx selects if the transmit encoder is enabled or bypassed. when enc bypx = 1, the transmit enc oder is enabled. when encbypx = 0, the transmit encoder is bypass ed and raw 10-bit charac ters are transmitted. txcksela txckselb txckselc txckseld transmit clock select . the initialization value of the txckselx latc h = 1. txckselx selects the clock source used to write data into the transmit input regi ster. when txckselx = 1, t he associated input register, txdx[7:0] and txctx[1:0], is clocked by refclkx . in this mode, the phase alignment buffer in the transmit path is bypassed. when txckselx = 0, the associated txclkx is used to clock in the input registers, txdx[7:0] and txctx[1:0]. txratea txrateb txratec txrated transmit pll clock rate select . the initialization value of the txra tex latch = 0. txratex is used to select the clock multiplier for the transmit pll. when txratex = 0, each transmit pll multiples the associated refclkx input by 10 to generate the seri al bit-rate clock. when txratex = 0, the txclkox output clocks are full-rate clocks and follow the frequen cy and duty cycle of the associated refclkx input. when txratex = 1, each transmit pll multiplies th e associated refclkx input by 20 to generate the serial bit-rate clock. when txratex = 1, the txclko x output clocks are twice the frequency rate of the refclkx input. when txckselx = 1 and txratex = 1, the transmit data input s are captured using both the rising and falling edges of refclkx. txratex = 1 and spdselx is low, is an invalid state and this combination is reserved. rfena rfenb rfenc rfend reframe enable . the initialization value of the rfenx latch = 1. rfenx selects if the receiver framer is enabled or disabled. when rfenx = 1, the associated cha nnel?s framer is enabled to frame per the presently enabled framing mode and selected framing character. w hen rfenx = 0, the associated channel?s framer is disabled, and no received bits alters the frame offset. rxpllpda rxpllpdb rxpllpdc rxpllpdd receive channel enable . the initialization value of the rxpllpdx latch = 0. rxpllpdx selects if the associated receive channel is enabled or powered-do wn. when rxpllpdx = 0, the associated pll and analog circuitry is powered-down. when rxpllpdx = 1, the associated pll and analog circuitry is enabled. rxbista rxbistb rxbistc rxbistd receive bist disabled . the initialization value of the rxbistx latc h = 1. rxbistx selects if receive bist is disabled or enabled. when rxbistx = 1, the receiver bist function is disabled. when rxbistx = 0, the receive bist function is enabled. txbista txbistb txbistc txbistd transmit bist disabled . the initialization value of the txbistx latch = 1. txbistx selects if the transmit bist is disabled or enabled. when txbistx = 1, the transmit bist function is disabled. when txbistx = 0, the transmit bist function is enabled. oe2a oe2b oe2c oe2d secondary differential serial data output driver enable . the initialization value of the oe2x latch = 0. oe2x selects if the out2 secondary differential outpu t drivers are enabled or disabled. when oe2x = 1, the associated serial data output driver is enabled allowing da ta to be transmitted from the transmit shifter. when oe2x = 0, the associated serial data ou tput driver is disabled. when a driv er is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associat ed internal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. table 9. device configuration and control latch descriptions (continued) name signal description
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 21 of 43 device configuration strategy the following is a series of ordered events needed to load the configuration latches on a per channel basis: 1. pulse reset low after device power-up. this operation resets all four channels. 2. set the static receiver latch bank for the target channel. may be performed using a global ope ration, if the application permits it. [optional step if th e default settings match the desired configuration.] 3. set the static transmitter latc h bank for the target channel. may be performed using a global operation, if the appli- cation permits it. [optional step if the default settings match the desired configuration.] 4. set the dynamic bank of latches for the target channel. enable the receive plls and transmit channels. may be performed using a global oper ation, if the application permits it. [required step.] 5. reset the phase alignment buffer for the target channel. may be performed using a global operation, if the appli- cation permits it. [optional if phase align buffer is bypassed.] when a receive channel is configured with the decoder bypassed and the receive clock selected as re covered clock in half-rate mode (decbypx = 0, rxratex = 1, rxckselx = 0), the channel cannot be dynamically reconfigured to enable the decoder with rxclkx selected as the refclkx (decbypx = 1, rxckselx = 1). if such a change is desired, a global reset should be performed and all channels should be reconfigured to the desired settings. oe1a oe1b oe1c oe1d primary differential serial data output driver enable . the initialization value of the oe1x latch = 0. oe1x selects if the out1 primary differenti al output drivers are enabled or dis abled. when oe1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. when oe1x = 0, the associated serial data output driver is disabled. w hen a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logi c for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. pabrsta pabrstb pabrstc pabrstd transmit clock phase alignment buffer reset . the initialization value of the pabrstx latch = 1. the pabrstx is used to re-center the transmit phase align buffer. when the configuration latch pabrstx is written as a 0, the phase of the txclkx input clock re lative to its associated re fclkx+/- is initialized. pabrst is an asynchronous input, but is sampled by each txclkx to synchronize it to the internal clock domain. pabrstx is a self clearing latch. this elimin ates the requirement of wr iting a 1 to complete the initialization of the phase alignment buffer. glen[11..0] global enable . the initialization value of the glenx latch = 1. the glenx is used to reconfigure several channels simultaneously in applications where severa l channels may have the same configuration. when glenx = 1 for a given address, that address is allowed to participate in a global configuration. when glenx = 0 for a given address, that address is disabl ed from participating in a global configuration. fglen[2..0] force global enable . the initialization value of the fglenx latc h is na. the fglenx la tch forces a global enable no matter what the setting is on the glenx la tch. if fglenx = 1 for t he associated global channel, fglen forces the global update of the target latch banks. table 9. device configuration and control latch descriptions (continued) name signal description
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 22 of 43 jtag support the cyp(v)(w)15g0403dxb contains a jtag port to allow system level diagnosis of device interconnect. of the available jtag modes, boundary scan, and bypass are supported. this capability is present only on the lvttl inputs and outputs and the refclkx clock input. the high-speed serial inputs and outputs are not part of the jtag test chain. 3-level select inputs each 3-level select inputs reports as two bits in the scan register. these bits report t he low, mid, and high state of the associated input as 00, 10, and 11 respectively jtag id the jtag device id for the cyp(v)(w)15g0403dxb is ?0c810069?x. table 10. device control latch configuration table addr channel type data7 data6 data5 data4 data3 data2 data1 data0 reset value 0 (0000b) a s rfmodea[1] rfmodea[0] framchara decmodea decbypa rxcksela rxratea glen0 10111111 1 (0001b) a s sdasel2a[1] sdasel2a[0] sdasel1a[1] sdasel1a[0] encbypa txcksela txratea glen1 10101101 2 (0010b) a d rfena rxpllpda rxbista txbista oe2a oe1a pabrsta glen2 10110011 3 (0011b) b s rfmodeb[1] rfmodeb[0] framcharb decmodeb decbypb rxckselb rxrateb glen3 10111111 4 (0100b) b s sdasel2b[1] sdasel2b[0] sdasel1b[1] sdasel1b[0] encbypb txckselb txrateb glen4 10101101 5 (0101b) b d rfenb rxpllpdb rxbistb txbistb oe2b oe1b pabrstb glen5 10110011 6 (0110b) c s rfmodec[1] rfmodec[0] framcharc decmodec decbypc rxckselc rxratec glen6 10111111 7 (0111b) c s sdasel2c[1] sdasel2c[0] sdasel1c[1] sdasel1c[0] encbypc txckselc txratec glen7 10101101 8 (1000b) c d rfenc rxpllpdc rxbistc txbistc oe2c oe1c pabrstc glen8 10110011 9 (1001b) d s rfmoded[1] rfmoded[0] framchard decmoded decbypd rxckseld rxrate d glen9 10111111 10 (1010b) d s sdasel2d[1] sdasel2d[0] sdasel1d[1] sdasel1d[0] encbypd txckseld txrated glen10 10101101 11 (1011b) d d rfend rxpllpdd rxbistd txbistd oe2d oe1d pabrstd glen11 10110011 12 (1100b) global s rfmodegl[1] rfmode gl[0] framchargl decmodegl decbypgl rxckselgl rxrateg l fglen0 n/a 13 (1101b) global s sdasel2gl[1] sdasel2gl[ 0] sdasel1gl[1] sdasel1gl[0 ] encbpgl txckselgl txrateg l fglen1 n/a 14 (1110b) global d rfengl rxpllpdgl rxbistgl txbistgl oe2gl oe1gl pabrstg l fglen2 n/a 15 (1111b) mask d d7 d6 d5 d4 d3 d2 d1 d0 11111111
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 23 of 43 table 11. receive character status bits rxstx[2:0] priority description normal status receive bist status (receive bist = enabled) 000 7 normal character received . the valid data character on the output bus meets all the formatting requirements of data characters listed in ta ble 15 . bist data compare . character compared correctly. 001 7 special code detected . the valid special character on the output bus meets all the formatting requirements of special code characters listed in table 16 , but is not the presently selected framing character or a decoder violation indication. bist command compare . character compared correctly. 010 2 receive elasticity buffer underrun/overrun error . the receive buffer was not able to add/drop a k28.5 or framing character bist last good . last character of bist sequence detected and valid. 011 5 framing character detected . this indicates that a character matching the patterns identified as a framing character (as selected by framcharx) was detected. the decoded value of this character is present in the associated output bus. 100 4 codeword violation . the character on the output bus is a c0.7. this indicates that the received character cannot be decoded into any valid character. bist last bad . last character of bist sequence detected invalid. 101 1 loss of sync . this indicates a pll out of lock condition bist start . receive bist is enabled on this channel, but character compares have not yet commenced. this also indicates a pll out of lock condition, and elasticity buffer overflow/underflow conditions. 110 6 running disparity error . the character on the output bus is a c4.7, c1.7, or c2.7. bist error . while comparing characters, a mismatch was found in one or more of the decoded character bits. 111 3 reserved bist wait . the receiver is comparing characters. but has not yet found the start of bist character to enable the lfsr.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 24 of 43 receive bist detected low monitor data received rxstx = bist_start (101) no rx pll out of lock yes, rxstx = bist_data_compare (000) / bist_command_compare (001) compare next character auto-abort condition mismatch end-of-bist state yes, rxstx = bist_last_bad (100) yes no no, rxstx = bist_error (110) data or command match command rxstx = bist_command_compare (001) end-of-bist state data yes, rxstx = bist_last_good (010) no rxstx = bist_data_compare (000) figure 2. receive bist state machine elasticity buffer error start of bist detected rxstx = bist_wait (111) yes rxstx = bist_start (101) no
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 25 of 43 maximum ratings above which the useful life may be impaired. user guidelines only, not tested storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ............... ?0.5v to +3.8v dc voltage applied to lvttl outputs in high-z state .......................................?0.5v to v cc + 0.5v output current into lvttl outputs (low)..................60 ma dc input voltage....................................?0.5v to v cc + 0.5v static discharge voltage.......................................... > 2000 v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma power-up requirements the cyp(v)(w)15g0403dxb requires one power-supply. the voltage on any input or i/o pin cannot exceed the power pin during power-up. operating range range ambient temperature v cc commercial 0c to +70c +3.3v 5% industrial ?40c to +85c +3.3v 5% cyp(v)(w)15g0403dxb dc electrical characteristics parameter description test conditions min. max. unit lvttl-compatible outputs v oht output high voltage i oh = ? 4 ma, v cc = min. 2.4 v v olt output low voltage i ol = 4 ma, v cc = min. 0.4 v i ost output short circuit current v out = 0v [10] , v cc = 3.3v ?20 ?100 ma i ozl high-z output leakage current v out = 0v, v cc ?20 20 a lvttl-compatible inputs v iht input high voltage 2.0 v cc + 0.3 v v ilt input low voltage ?0.5 0.8 v i iht input high current refclkx input, v in = v cc 1.5 ma other inputs, v in = v cc +40 a i ilt input low current refclkx input, v in = 0.0v ?1.5 ma other inputs, v in = 0.0v ?40 a i ihpdt input high current with internal pull-down v in = v cc +200 a i ilput input low current with internal pull-up v in = 0.0v ?200 a lvdiff inputs: refclkx v diff [11] input differential voltage 400 v cc mv v ihhp highest input high voltage 1.2 v cc v v illp lowest input low voltage 0.0 v cc /2 v v comref [12] common mode range 1.0 v cc ? 1.2v v 3-level inputs v ihh three-level input high voltage min. v cc max. 0.87 * v cc v cc v v imm three-level input mid voltage min. v cc max. 0.47 * v cc 0.53 * v cc v v ill three-level input low voltage min. v cc max. 0.0 0.13 * v cc v i ihh input high current v in = v cc 200 a i imm input mid current v in = v cc /2 ?50 50 a i ill input low current v in = gnd ?200 a differential cml serial outputs: outa1 , outa2 , outb1 , outb2 , outc1 , outc2 , outd1 , outd2 v ohc output high voltage (v cc referenced) 100 ? differential load v cc ? 0.5 v cc ? 0.2 v 150 ? differential load v cc ? 0.5 v cc ? 0.2 v notes: 10. tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 11. this is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 o r logic-0. a logic-1 exists when the true (+) input is more positive than the complement ( ? ) input. a logic-0 exists when the complement ( ? ) input is more positive than true (+) input. 12. the common mode range defines the allowable range of refclkx+ and refclkx ? when refclkx+ = refclkx ? . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 26 of 43 v olc output low voltage (v cc referenced) 100 ? differential load v cc ? 1.4 v cc ? 0.7 v 150 ? differential load v cc ? 1.4 v cc ? 0.7 v v odif output differential voltage |(out+) ? (out ? )| 100 ? differential load 450 900 mv 150 ? differential load 560 1000 mv differential serial line receiver inputs: ina1 , ina2 , inb1 , inb2 , inc1 , inc2 , ind1 , ind2 v diffs [11] input differential voltage |(in+) ? (in ? )| 100 1200 mv v ihe highest input high voltage v cc v v ile lowest input low voltage v cc ? 2.0 v i ihe input high current v in = v ihe max. 1350 a i ile input low current v in = v ile min. ?700 a vi com [13] common mode input range ((v cc ? 2.0v)+0.5)min, (v cc ? 0.5v) max. +1.25 +3.1 v power supply typ. max. i cc [14, 15] max power supply current refclkx = max commercial 910 1270 ma industrial 1320 ma i cc [14, 15] typical power supply current refclkx = 125 mhz commercial 900 1270 ma industrial 1320 ma cyp(v)(w)15g0403dxb dc electrical characteristics (continued) parameter description test conditions min. max. unit ac test loads and waveforms notes: 13. the common mode range defines the allowable range of input+ and input ? when input+ = input ? . this marks the zero-crossing between the true and complement inputs as the signal swit ches between a logic-1 and a logic-0. 14. maximum i cc is measured with v cc = max, rfenx = 0, t a = 25c, with all channels and serial line driver s enabled, sending a continuous alternating 01 pattern, and outputs unloaded. 15. typical i cc is measured under similar conditions except with v cc = 3.3v, t a = 25c, rfenx = 0, with all channels enabled and one serial line driver per transmit channel sending a continuous alternating 01 pattern. the redundant outputs on each channel are powered down and the pa rallel outputs are unloaded. 16. cypress uses constant current (ate) load configurations and forcing functions. this fi gure is for reference only. 17. the lvttl switching threshold is 1.4v. al l timing references are made relative to where the signal edges cross the threshold voltage. 2.0v 0.8v gnd 2.0v 0.8v 80% 20% 80% 20% r l (includes fixture and probe capacitance) 3.0v v th =1.4v 270 ps 270 ps [17] v th =1.4v 3.3v r1 r2 r1 = 590 ? r2 = 435 ? (includes fixture and probe capacitance) c l 7 pf (a) lvttl output test load r l = 100 ? (b) cml output test load c l (c) lvttl input test waveform (d) cml/lvpecl input test waveform 1ns 1 ns v ihe v ile v ihe v ile [16] [16]
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 27 of 43 cyp(v)(w)15g0403dxb ac electrical characteristics parameter description min. max unit cyp(v)(w)15g0403dxb transmitter lv ttl switching characteristics over the operating range f ts txclkx clock cycle frequency 19.5 150 [18] mhz t txclk txclkx period=1/f ts 6.66 [19] 51.28 ns t txclkh [20] txclkx high time 2.2 ns t txclkl [20] txclkx low time 2.2 ns t txclkr [20, 21, 22, 23] txclkx rise time 0.2 1.7 ns t txclkf [20, 21, 22, 23] txclkx fall time 0.2 1.7 ns t txds transmit data set-up time to txclkx (txckselx 0) 2.2 ns t txdh transmit data hold time from txclkx (txckselx 0) 1.0 ns f tos txclkox clock frequency = 1x or 2x refclkx frequency 19.5 150 [18] mhz t txclko txclkox period=1/f tos 6.66 [19] 51.28 ns t txclkod txclko duty cycle centered at 60% high time ?1.9 0 ns cyp(v)(w)15g0403dxb receiver lv ttl switching characteristics over the operating range f rs rxclkx clock output frequency 9.75 150 [18] mhz t rxclkp rxclkx period = 1/f rs 6.66 [19] 102.56 ns t rxclkd rxclkx duty cycle centered at 50% (full rate and half rate when rxckselx = 0) ?1.0 +1.0 ns t rxclkr [20] rxclkx rise time 0.3 1.2 ns t rxclkf [20] rxclkx fall time 0.3 1.2 ns t rxdv? [24] status and data valid time to rxclkx (rxratex = 0, rxckselx = 0) (full rate) 5ui ? 2.0 [25] ns status and data valid time to rxclkx (rxratex = 1, rxckselx = 0) (half rate) 5ui ? 1.3 [25] ns t rxdv+ [24] status and data valid time to rxclkx (rxratex = 0, rxckselx = 0) (full rate) 5ui?1.8 [25] ns status and data valid time to rx clkx (rxratex = 1, rxckselx =0) (half rate) 5ui ? 2.6 [25] ns cyp(v)(w)15g0403dxb refclkx switching characteristics over the operating range f ref refclkx clock frequency 19.5 150 [18] mhz t refclk refclkx period = 1/f ref 6.66 [19] 51.28 ns t refh refclkx high time (txr atex = 1)(half rate) 5.9 [26] ns refclkx high time (txr atex = 0)(full rate) 2.9 [20] ns t refl refclkx low time (txratex = 1)(half rate) 5.9 [26] ns refclkx low time (txratex = 0)(full rate) 2.9 [20] ns t refd [27] refclkx duty cycle 30 70 % t refr [20, 21, 22, 23] refclkx rise time (20%?80%) 2 ns t reff [20, 21, 22, 23] refclkx fall time (20%?80%) 2 ns notes: 18. this parameter is 154 mhz for cyw15g0403dxb. 19. this parameter is 6.49 ns for cyw15g0403dxb. 20. tested initially and after any design or process changes that may affect these parameters, but not 100% tested. 21. the ratio of rise time to falling time must not vary by greater than 2:1. 22. for a given operating frequency, neither rise or fall specific ation can be greater than 20% of the clock-cycle period or the data sheet maximum time. 23. all transmit ac timing parameters measured with 1 ns typical rise time and fall time. 24. parallel data output specifications are only valid if all outputs are loaded with similar dc and ac loads. 25. receiver ui (unit interval) is calculated as 1/(f ref * 20) (when txratex = 1) or 1/(f ref * 10) (when txratex = 0). in an operating link this is equivalent to t b . 26. if refclkx is selected as receive interface clock (rxckselx=1) , then this parameter has to be greater than or equal to 6.3 n s. 27. the duty cycle specification is a simultaneous condition with the t refh and t refl parameters. this means that at fast er character rates the refclkx duty cycle cannot be as large as 30%?70%.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 28 of 43 t trefds transmit data set-up time to refclkx - full rate (txratex = 0, txckselx = 1) 2.4 ns transmit data set-up time to refclkx - half rate (txratex = 1, txckselx = 1) 2.3 ns t trefdh transmit data hold time from refclkx - full rate (txratex = 0, txckselx = 1) 1.0 ns transmit data hold time from refclkx - half rate (txratex = 1, txckselx = 1) 1.6 ns t rrefda receive data access time to refclkx (rxckselx = 1) 9.7 [28] ns t rrefdw receive data valid time window (rxckselx = 1) 10ui ? 5.8 ns t refxdv? received data valid time to rxclk when rxckselx = 1 (txratex = 0, rxratex = 0) 10ui [25] ? 6.16 ns received data valid time to rxclk when rxckselx = 1 (txratex = 0, rxratex = 1) 5ui ? 2.53 [29] ns received data valid time to rxclk when rxckselx = 1 (txratex = 1) 10ui ? 5.86 [29] ns t refxdv+ received data valid time from rxclk when rxckselx = 1 (txratex = 0, rxratex = 0) 1.4 ns received data valid time from rxclk when rxckselx = 1 (txratex = 0, rxratex = 1) 5ui ? 1.83 [29] ns received data valid time from rxclk when rxckselx = 1 (txratex = 1) 1.0 [29] ns t refrx [30] refclkx frequency referenced to received clock period ?0.15 +0.15 % cyp(v)(w)15g0403dxb bus configurat ion write timing characteristics over the operating range t datah bus configuration data hold 0 ns t datas bus configuration data set-up 10 ns t wrenp bus configuration wren pulse width 10 ns cyp(v)(w)15g0403dxb jtag te st clock characteristics over the operating range f tclk jtag test clock frequency 20 mhz t tclk jtag test clock period 50 ns cyp(v)(w)15g0403dxb device reset characteristics over the operating range t rst device reset pulse width 30 ns cyp(v)(w)15g0403dxb transmit serial outputs and tx pll characteristics over the operating range parameter description condition min. max. unit t b bit time 5128 666 ps t rise [20] cml output rise time 20 ? 80% (cml test load) spdselx = high 60 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000 ps notes: 28. since this timing parameter is greater than the minimum time period of refclk it sets an upper limit to the frequency in whi ch refclkx can be used to clock the receive data out of the output register. for predictable timi ng, users can use this parameter only if refclk period is grea ter than sum of t rrefda and set- up time of the upstream device. when this condition is not tr ue, rxclkx (a buffered or divided version of refclk when rxckselx = 1) could be used to clock the receive data out of the device. 29. measured using a 50% duty cycle reference clock. 30. refclkx has no phase or frequency relationship with the recovere d clock and only acts as a centering reference to reduce clo ck synchronization time. refclkx must be within 1500 ppm (0.15%) of the remote transmitter?s pll reference (refclkx) frequency. although transmitting to a hotlink ii receiver channel necessitates the frequency difference between the transmitte r and receiver reference clocks to be within 1500 ppm, the stability of the crystal needs to be within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. for example, to be ieee 802.3z gigabit ethernet compliant, the frequency stabili ty of the crystal needs to be within 100 ppm.l. cyp(v)(w)15g0403dxb ac electrical characteristics (continued) parameter description min. max unit
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 29 of 43 t fall [20] cml output fall time 80 ? 20% (cml test load) spdselx = high 60 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000 ps t dj [20, 31, 33] deterministic jitter (peak-peak) [34] ieee 802.3z 27 ps t rj [20, 32, 33] random jitter ( ) [34] ieee 802.3z 11 ps t refj [20] refclkx jitter tolerance / phase noise limits tbd t txlock transmit pllx lock to refclkx 200 s cyp(v)(w)15g0403dxb receive serial inputs and cdr pll characteristics over the operating range t rxlock receive pll lock to input data stream (cold start) 376k ui receive pll lock to input data stream 376k ui t rxunlock receive pll unlock rate 46 ui t jtol [20] to ta l j i t t e r to l e r a n c e [34] ieee 802.3z 600 ps t djtol [20] deterministic jitter tolerance [34] ieee 802.3z 370 ps capacitance [20] parameter description test conditions max. unit c inttl ttl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 7 pf c inpecl pecl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 4 pf cyp(v)(w)15g0403dxb ac electrical characteristics (continued) parameter description min. max unit cyp(v)(w)15g0403dxb hotlink ii transmitter switching waveforms notes: 31. while sending continuous k28.5s, outputs loaded to a balanced 100 ? load, measured at the cross point of differential outputs, over the operating range. 32. while sending continuous k28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to refclkx input, over the operating range. 33. total jitter is calculated at an assumed ber of 1e ? 12. hence: total jitter (t j ) = (t rj * 14) + t dj . 34. also meets all jitter generation and jitter tolerance requirem ents as specified by smpte 259m, smpte 292m, escon, ficon, fib re channel, and dvb-asi. txclkx txdx[7:0], txctx[1:0], t txdh t txds t txclk t txclkh t txclkl transmit interface write timing txclkx selected refclkx transmit interface t refclk t refh t refl t trefds t trefdh write timing txratex = 0 txdx[7:0], txctx[1:0], refclkx selected
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 30 of 43 notes: 35. when refclkx is configured for half-rate operation (txrate = 1) and data is captured using refclkx instead of a txclkx cloc k. data is captured using both the rising and falling edges of refclkx. 36. the txclkox output remains at the characte r rate regardless of the st ate of txrate and does no t follow the duty cycle of ref clkx. 37. the rising edge of txclkox output has no dire ct phase relationship to the refclkx input. cyp(v)(w)15g0403dxb hotlink ii transmitter switching waveforms (continued) t trefdh transmit interface write timing txratex = 1 refclkx t refclk t refl t refh note 35 txdx[7:0], txctx[1:0], t trefds t trefds t trefdh refclkx selected txclkox t txclko transmit interface txclkox timing txratex = 1 (internal) refclkx t refclk t refl t refh note 36 note 37 txclkox t txclko t txoh t txol transmit interface txclkox timing refclkx note36 note37 t refclk t refh t refl txratex = 0
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 31 of 43 switching waveforms for the cyp(v)(w)15g0403dxb hotlink ii receiver note: 38. when operated with a half-rate refclkx, the set-up and hold specif ications for data relative to rxclkx are relative to both rising and falling edges of the respective clock output 39. txerrx is synchronous to rxclkx only when rxclkx is selected as refclk. refclkx rxdx[7:0], rxstx[2:0], t refclk t refh t refl receive interface read timing full-rate rxclkx rxclkx t refxdv+ t refxdv ? t rrefda refclkx selected t rrefdw t rrefdw txerrx [ 39 ] refclkx rxdx[7:0], rxstx[2:0], t refclk t refh t refl receive interface read timing half-rate rxclkx t rrefda rxclkx t refxdv+ t refxdv ? note 38 t rrefda refclkx selected t rrefdw t rrefdw txerrx [ 39 ] rxclkx+ rxdx[7:0], rxstx[2:0], t rxdv+ t rxclkp receive interface read timing rxratex = 0 rxclkx? t rxdv ? recovered clock selected
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 32 of 43 switching waveforms for the cyp(v)(w)15g0403dxb hotlink ii receiver rxclkx+ rxdx[7:0], rxstx[2:0] t rxdv+ t rxdv ? t rxclkp receive interface read timing rxratex = 1 rxclkx? recovered clock selected addr[3:0] t datas bus configuration write timing data[7:0] wren t datah t wrenp
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 33 of 43 table 12. package coordinate signal allocation ball id signal name signal type ball id signal name signal type ball id signal name signal type a01 inc1? cml in c07 ulcc lvttl in pu f17 nc no connect a02 outc1? cml out c08 gnd ground f18 rxstb[1] lvttl out a03 inc2? cml in c09 data[7] lvtt l in pu f19 txclkob lvttl out a04 outc2? cml out c10 data[5] lvt tl in pu f20 rxstb[0] lvttl out a05 vcc power c11 data[3] lvttl in pu g01 txdc[7] lvttl in a06 ind1? cml in c12 data[1] lvttl in pu g02 wren lvttl in pu a07 outd1? cml out c13 gnd ground g03 txdc[4] lvttl in a08 gnd ground c14 nc no connect g04 txdc[1] lvttl in a09 ind2? cml in c15 spdseld 3-l evel sel g17 spdselb 3-level sel a10 outd2? cml out c16 vcc p ower g18 lpenc lvttl in pd a11 ina1? cml in c17 ldtden lvttl in pu g19 spdsela 3-level sel a12 outa1? cml out c18 trst lvtt l in pu g20 rxdb[1] lvttl out a13 gnd ground c19 lpend lvttl in pd h01 gnd ground a14 ina2? cml in c20 tdo lvttl 3-s out h02 gnd ground a15 outa2? cml out d01 tclk lvttl in pd h03 gnd ground a16 vcc power d02 reset lvttl in pu h04 gnd ground a17 inb1? cml in d03 inseld lvttl in h17 gnd ground a18 outb1? cml out d04 insela lvttl in h18 gnd ground a19 inb2? cml in d05 vcc power h19 gnd ground a20 outb2? cml out d06 ulca lvttl in pu h20 gnd ground b01 inc1+ cml in d07 spdselc 3-l evel sel j01 txctc[1] lvttl in b02 outc1+ cml out d08 gnd ground j02 txdc[5] lvttl in b03 inc2+ cml in d09 data[6] lvttl in pu j03 txdc[2] lvttl in b04 outc2+ cml out d10 data[4] lvttl in pu j04 txdc[3] lvttl in b05 vcc power d11 data[2] lvttl in pu j17 rxstb[2] lvttl out b06 ind1+ cml in d12 data[0] lvttl in pu j18 rxdb[0] lvttl out b07 outd1+ cml out d13 gnd ground j19 rxdb[5] lvttl out b08 gnd ground d14 lpenb lvttl in pd j20 rxdb[2] lvttl out b09 ind2+ cml in d15 ulcb lvttl in pu k01 rxdc[2] lvttl out b10 outd2+ cml out d16 vcc power k02 refclkc? pecl in b11 ina1+ cml in d17 lpena lvttl in pd k03 txctc[0] lvttl in b12 outa1+ cml out d18 lten1 lvttl in pd k04 txclkc lvttl in pd b13 gnd ground d19 scanen2 lvttl in pd k17 rxdb[3] lvttl out b14 ina2+ cml in d20 tmen3 lvttl in pd k18 rxdb[4] lvttl out b15 outa2+ cml out e01 vcc power k19 rxdb[7] lvttl out b16 vcc power e02 vcc power k20 lfib lvttl out b17 inb1+ cml in e03 vcc power l01 rxdc[3] lvttl out b18 outb1+ cml out e04 vcc power l02 refclkc+ pecl in b19 inb2+ cml in e17 vcc power l03 lfic lvttl out b20 outb2+ cml out e18 vcc power l04 txdc[6] lvttl in c01 tdi lvttl in pu e19 vcc power l17 rxdb[6] lvttl out c02 tms lvttl in pu e20 vcc power l18 rxclkb+ lvttl out c03 inselc lvttl in f01 rxdc[6] lvttl out l19 rxclkb? lvttl out
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 34 of 43 c04 inselb lvttl in f02 rxdc[7] lvttl out l20 txdb[6] lvttl in c05 vcc power f03 txdc[0] lvtt l in m01 rxdc[4] lvttl out c06 ulcd lvttl in pu f04 nc no connect m02 rxdc[5] lvttl out m03 nc no connect u03 txdd[2] lvttl in w03 lfid lvttl out m04 txerrc lvttl out u04 txctd[1] lvttl in w04 rxclkd? lvttl out m17 refclkb+ pecl in u05 vcc power w05 vcc power m18 refclkb? pecl in u06 rxdd[2] lvttl out w06 rxdd[4] lvttl out m19 txerrb lvttl out u07 rxdd[1] lvttl out w07 rxstd[1] lvttl out m20 txclkb lvttl in pd u08 gnd ground w08 gnd ground n01 gnd ground u09 txcta[1] lvttl in w09 addr [3] lvttl in pu n02 gnd ground u10 addr [0] lvttl in pu w10 addr [1] lvttl in pu n03 gnd ground u11 refclkd? pecl in w11 rxclka+ lvttl out n04 gnd ground u12 txda[1] lvttl in w12 txerra lvttl out n17 gnd ground u13 gnd ground w13 gnd ground n18 gnd ground u14 txda[4] lv ttl in w14 txda[2] lvttl in n19 gnd ground u15 txcta[0] lvttl in w15 txda[6] lvttl in n20 gnd ground u16 vcc power w16 vcc power p01 rxdc[1] lvttl out u17 rxda[2] lvttl out w17 lfia lvttl out p02 rxdc[0] lvttl out u18 txctb[0] lvttl in w18 refclka+ pecl in p03 rxstc[0] lvttl out u19 rxsta[2] lvttl out w19 rxda[4] lvttl out p04 rxstc[1] lvttl out u20 rxsta[1] lvttl out w20 rxda[1] lvttl out p17 txdb[5] lvttl in v01 txdd[3] lvttl in y01 txdd[6] lvttl in p18 txdb[4] lvttl in v02 txdd[4] lvttl in y02 txclkd lvttl in pd p19 txdb[3] lvttl in v03 txctd[0] lvttl in y03 rxdd[7] lvttl out p20 txdb[2] lvttl in v04 rxdd[6] lvttl out y04 rxclkd+ lvttl out r01 rxstc[2] lvttl out v05 vcc power y05 vcc power r02 txclkoc lvttl out v06 rxdd[3] lvttl out y06 rxdd[5] lvttl out r03 rxclkc+ lvttl out v07 rxstd[0] lvttl out y07 rxdd[0] lvttl out r04 rxclkc? lvttl out v08 gnd ground y08 gnd ground r17 txdb[1] lvttl in v09 rxstd[2] lv ttl out y09 txclkod lvttl out r18 txdb[0] lvttl in v10 addr [2 ] lvttl in pu y10 nc no connect r19 txctb[1] lvttl in v11 refclkd + pecl in y11 txclka lvttl in pd r20 txdb[7] lvttl in v12 txclkoa lvttl out y12 rxclka? lvttl out t01 vcc power v13 gnd ground y13 gnd ground t02 vcc power v14 txda[3] lvttl in y14 txda[0] lvttl in t03 vcc power v15 txda[7] lvttl in y15 txda[5] lvttl in t04 vcc power v16 vcc power y16 vcc power t17 vcc power v17 rxda[7] lvttl out y17 txerrd lvttl out t18 vcc power v18 rxda[3] lvttl out y18 refclka? pecl in t19 vcc power v19 rxda[0] lvttl out y19 rxda[6] lvttl out t20 vcc power v20 rxsta[0] lvttl out y20 rxda[5] lvttl out u01 txdd[0] lvttl in w01 txdd[5] lvttl in u02 txdd[1] lvttl in w02 txdd[7] lvttl in table 12. package coordinate signal allocation (continued) ball id signal name signal type ball id signal name signal type ball id signal name signal type
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 35 of 43 x3.230 codes and notation conventions information transmitted over a serial link is encoded eight bits at a time into a 10-bit transmission character and then sent serially, bit by bit. information received over a serial link is collected ten bits at a time, and those transmission characters that are used for data characters are decoded into the correct eight-bit codes. the 10-bit transmission code supports all 256 8-bit combinations. some of the remaining transmission characters (special characters) are used for functions other than data transmission. the primary use of a transmission code is to improve the transmission characteristics of a serial link. the encoding defined by the transmission code ensures that sufficient transitions are present in the serial bit stream to make clock recovery possible at the receiver. such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information. in addition, some special characters of the trans- mission code selected by fibre channel standard contain a distinct and easily recognizable bit pattern that assists the receiver in achieving character alignment on the incoming bit stream. notation conventions the documentation for the 8b/10b transmission code uses letter notation for the bits in an 8-bit byte. fibre channel standard notation uses a bit notation of a, b, c, d, e, f, g, h for the 8-bit byte for the raw 8-bit data, and the letters a, b, c, d, e, i, f, g, h, j for encoded 10-bit data. there is a correspon- dence between bit a and bit a, b and b, c and c, d and d, e and e, f and f, g and g, and h and h. bits i and j are derived, respectively, from (a,b,c,d,e) and (f,g,h). the bit labeled a in the description of the 8b/10b transmission code corresponds to bit 0 in the numbering scheme of the fc- 2 specification, b corresponds to bit 1, as shown below. fc-2 bit designation? 76543210 hotlink d/q designation? 76543210 8b/10b bit designation? h g f e d c b a to clarify this correspondence, the following example shows the conversion from an fc-2 valid data byte to a transmission character. fc-2 45h bits: 7654 3210 0100 0101 converted to 8b/10b notation, not e that the order of bits has been reversed): data byte name d5.2 bits: abcde fgh 10100 010 translated to a transmission character in the 8b/10b trans- mission code: bits: abcdei fghj 101001 0101 each valid transmission character of the 8b/10b trans- mission code has been given a name using the following convention: cxx.y, where c is used to show whether the trans- mission character is a data character (c is set to d, and sc/d = low) or a special character (c is set to k, and sc/d = high). when c is set to d, xx is the decimal value of the binary number composed of the bits e, d, c, b, and a in that order, and the y is the decimal value of the binary number composed of the bits h, g, and f in that order. when c is set to k, xx and y are derived by comparing the encoded bit patterns of the special character to those patterns derived from encoded valid data bytes and selecting the names of the patterns most similar to the encoded bit patterns of the special character. under the above conventions, the transmission character used for the examples above, is referred to by the name d5.2. the special character k29.7 is so named because the first six bits (abcdei) of this character make up a bit pattern similar to that resulting from the encoding of the unencoded 11101 pattern (29), and because the second four bits (fghj) make up a bit pattern similar to that re sulting from the encoding of the unencoded 111 pattern (7). note . this definition of the 10-bit transmission code is based on the following references, which describe the same 10-bit transmission code. a.x. widmer and p.a. franasze k. ?a dc-balanced, parti- tioned-block, 8b/10b transmission code? ibm journal of research and development, 27, no. 5: 440-451 (september, 1983). u.s. patent 4,486,739. peter a. franaszek and albert x. widmer. ?byte-oriented dc balanced (0.4) 8b/10b parti- tioned block transmission code? (december 4, 1984). fibre channel physical and signaling interface (ans x3.230- 1994 ansi fc-ph standard). ibm enterprise systems ar chitecture/390 escon i/o interface (document number sa22-7202). 8b/10b transmission code the following information describes how the tables are used for both generating valid transmission characters (encoding) and checking the validity of received transmission characters (decoding). it also specifies the ordering rules followed when transmitting the bits within a character and the characters within any higher-level constructs specified by a standard. transmission order within the definition of the 8b/10b transmission code, the bit positions of the transmission characters are labeled a, b, c, d, e, i, f, g, h, j. bit ?a? is tran smitted first followed by bits b, c, d, e, i, f, g, h, and j in that order. note that bit i is transmitted between bit e and bit f, rather than in alphabetical order. valid and invalid transmission characters the following tables define the valid data characters and valid special characters (k characters), respectively. the tables are used for both generating valid transmission characters and checking the validity of received transmission characters. in the tables, each valid-data-byte or special- character-code entry has two columns that represent two transmission characters. the two columns correspond to the current value of the running disparity. running disparity is a binary parameter with either a negative (?) or positive (+) value. after powering on, the transmitter may assume either a positive or negative value for its initial running disparity. upon transmission of any transmission character, the transmitter selects the proper version of the transmission character
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 36 of 43 based on the current running disparity value, and the trans- mitter calculates a new value for its running disparity based on the contents of the transmitted character. special character codes c1.7 and c2.7 can be used to force the transmission of a specific special character with a specific running disparity as required for some special sequences in x3.230. after powering on, the receiver may assume either a positive or negative value for its initial running disparity. upon reception of any transmission character, the receiver decides whether the transmission character is va lid or invalid according to the following rules and tables and calculates a new value for its running disparity based on t he contents of the received character. the following rules for running disparity are used to calculate the new running-disparity value for transmission characters that have been transmitted and received. running disparity for a transmission character is calculated from sub-blocks, where the first six bits (abcdei) form one sub- block and the second four bits (fghj) form the other sub-block. running disparity at the beginning of the 6-bit sub-block is the running disparity at the end of the previous transmission character. running disparity at the beginning of the 4-bit sub- block is the running disparity at the end of the 6-bit sub-block. running disparity at the end of the transmission character is the running disparity at the end of the 4-bit sub-block. running disparity for the sub-blocks is calculated as follows: 1. running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. it is also positive at the end of the 6-bit sub-block if the 6-bit sub- block is 000111, and it is positive at the end of the 4-bit sub- block if the 4-bit sub-block is 0011. 2. running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. it is also negative at the end of the 6-bi t sub-block if the 6-bit sub- block is 111000, and it is negat ive at the end of the 4-bit sub- block if the 4-bit sub-block is 1100. 3. otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. use of the tables for generating transmission characters the appropriate entry in ta ble 15 for the valid data byte or table 16 for special character byte identify which trans- mission character is generated. the current value of the transmitter?s running disparity is used to select the trans- mission character from its corresponding column. for each transmission character transmitted, a new value of the running disparity is calculated. this new value is used as the transmitter?s current running disparity for the next valid data byte or special character byte encoded and transmitted. table 13 shows naming notations and examples of valid trans- mission characters. use of the tables for checking the validity of received transmission characters the column corresponding to the current value of the receiver?s running disparity is searched for the received transmission character. if the received transmission character is found in the proper column, then the trans- mission character is valid and the associated data byte or special character code is determined (decoded). if the received transmission character is not found in that column, then the transmission character is invalid. this is called a code violation. independent of the transmission character?s validity, the received transmission character is used to calculate a new value of running disparity. the new value is used as the receiver?s current running disparity for the next received transmission character. detection of a code violation does not necessarily show that the transmission character in which the code violation was detected is in error. code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the transmission character in which the error occurred. table 14 shows an example of this behavior. table 13. valid transmission characters data byte name d in or q out hex value 765 43210 d0.0 000 00000 00 d1.0 000 00001 01 d2.0 000 00010 02 . . . . . . . . d5.2 010 00101 45 . . . . . . . . d30.7 111 11110 fe d31.7 111 11111 ff table 14. code violations resulting from prior errors rd character rd character rd character rd transmitted data character ? d21.1 ? d10.2 ? d23.5 + transmitted bit stream ? 101010 1001 ? 010101 0101 ? 111010 1010 + bit stream after error ? 101010 1011 + 010101 0101 + 111010 1010 + decoded data character ? d21.0 + d10.2 + code violation +
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 37 of 43 table 15. valid data characters (txctx[0] = 0, rxstx[2:0] = 000) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj d0.0 000 00000 100111 0100 011000 1011 d0.1 001 00000 100111 1001 011000 1001 d1.0 000 00001 011101 0100 100010 1011 d1.1 001 00001 011101 1001 100010 1001 d2.0 000 00010 101101 0100 010010 1011 d2.1 001 00010 101101 1001 010010 1001 d3.0 000 00011 110001 1011 110001 0100 d3.1 001 00011 110001 1001 110001 1001 d4.0 000 00100 110101 0100 001010 1011 d4.1 001 00100 110101 1001 001010 1001 d5.0 000 00101 101001 1011 101001 0100 d5.1 001 00101 101001 1001 101001 1001 d6.0 000 00110 011001 1011 011001 0100 d6.1 001 00110 011001 1001 011001 1001 d7.0 000 00111 111000 1011 000111 0100 d7.1 001 00111 111000 1001 000111 1001 d8.0 000 01000 111001 0100 000110 1011 d8.1 001 01000 111001 1001 000110 1001 d9.0 000 01001 100101 1011 100101 0100 d9.1 001 01001 100101 1001 100101 1001 d10.0 000 01010 010101 1011 010101 0100 d10.1 001 01010 010101 1001 010101 1001 d11.0 000 01011 110100 1011 110100 0100 d11.1 001 01011 110100 1001 110100 1001 d12.0 000 01100 001101 1011 001101 0100 d12.1 001 01100 001101 1001 001101 1001 d13.0 000 01101 101100 1011 101100 0100 d13.1 001 01101 101100 1001 101100 1001 d14.0 000 01110 011100 1011 011100 0100 d14.1 001 01110 011100 1001 011100 1001 d15.0 000 01111 010111 0100 101000 1011 d15.1 001 01111 010111 1001 101000 1001 d16.0 000 10000 011011 0100 100100 1011 d16.1 001 10000 011011 1001 100100 1001 d17.0 000 10001 100011 1011 100011 0100 d17.1 001 10001 100011 1001 100011 1001 d18.0 000 10010 010011 1011 010011 0100 d18.1 001 10010 010011 1001 010011 1001 d19.0 000 10011 110010 1011 110010 0100 d19.1 001 10011 110010 1001 110010 1001 d20.0 000 10100 001011 1011 001011 0100 d20.1 001 10100 001011 1001 001011 1001 d21.0 000 10101 101010 1011 101010 0100 d21.1 001 10101 101010 1001 101010 1001 d22.0 000 10110 011010 1011 011010 0100 d22.1 001 10110 011010 1001 011010 1001 d23.0 000 10111 111010 0100 000101 1011 d23.1 001 10111 111010 1001 000101 1001 d24.0 000 11000 110011 0100 001100 1011 d24.1 001 11000 110011 1001 001100 1001 d25.0 000 11001 100110 1011 100110 0100 d25.1 001 11001 100110 1001 100110 1001 d26.0 000 11010 010110 1011 010110 0100 d26.1 001 11010 010110 1001 010110 1001 d27.0 000 11011 110110 0100 001001 1011 d27.1 001 11011 110110 1001 001001 1001 d28.0 000 11100 001110 1011 001110 0100 d28.1 001 11100 001110 1001 001110 1001 d29.0 000 11101 101110 0100 010001 1011 d29.1 001 11101 101110 1001 010001 1001 d30.0 000 11110 011110 0100 100001 1011 d30.1 001 11110 011110 1001 100001 1001 d31.0 000 11111 101011 0100 010100 1011 d31.1 001 11111 101011 1001 010100 1001
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 38 of 43 d0.2 010 00000 100111 0101 011000 0101 d0.3 011 00000 100111 0011 011000 1100 d1.2 010 00001 011101 0101 100010 0101 d1.3 011 00001 011101 0011 100010 1100 d2.2 010 00010 101101 0101 010010 0101 d2.3 011 00010 101101 0011 010010 1100 d3.2 010 00011 110001 0101 110001 0101 d3.3 011 00011 110001 1100 110001 0011 d4.2 010 00100 110101 0101 001010 0101 d4.3 011 00100 110101 0011 001010 1100 d5.2 010 00101 101001 0101 101001 0101 d5.3 011 00101 101001 1100 101001 0011 d6.2 010 00110 011001 0101 011001 0101 d6.3 011 00110 011001 1100 011001 0011 d7.2 010 00111 111000 0101 000111 0101 d7.3 011 00111 111000 1100 000111 0011 d8.2 010 01000 111001 0101 000110 0101 d8.3 011 01000 111001 0011 000110 1100 d9.2 010 01001 100101 0101 100101 0101 d9.3 011 01001 100101 1100 100101 0011 d10.2 010 01010 010101 0101 010101 0101 d10.3 011 01010 010101 1100 010101 0011 d11.2 010 01011 110100 0101 110100 0101 d11.3 011 01011 110100 1100 110100 0011 d12.2 010 01100 001101 0101 001101 0101 d12.3 011 01100 001101 1100 001101 0011 d13.2 010 01101 101100 0101 101100 0101 d13.3 011 01101 101100 1100 101100 0011 d14.2 010 01110 011100 0101 011100 0101 d14.3 011 01110 011100 1100 011100 0011 d15.2 010 01111 010111 0101 101000 0101 d15.3 011 01111 010111 0011 101000 1100 d16.2 010 10000 011011 0101 100100 0101 d16.3 011 10000 011011 0011 100100 1100 d17.2 010 10001 100011 0101 100011 0101 d17.3 011 10001 100011 1100 100011 0011 d18.2 010 10010 010011 0101 010011 0101 d18.3 011 10010 010011 1100 010011 0011 d19.2 010 10011 110010 0101 110010 0101 d19.3 011 10011 110010 1100 110010 0011 d20.2 010 10100 001011 0101 001011 0101 d20.3 011 10100 001011 1100 001011 0011 d21.2 010 10101 101010 0101 101010 0101 d21.3 011 10101 101010 1100 101010 0011 d22.2 010 10110 011010 0101 011010 0101 d22.3 011 10110 011010 1100 011010 0011 d23.2 010 10111 111010 0101 000101 0101 d23.3 011 10111 111010 0011 000101 1100 d24.2 010 11000 110011 0101 001100 0101 d24.3 011 11000 110011 0011 001100 1100 d25.2 010 11001 100110 0101 100110 0101 d25.3 011 11001 100110 1100 100110 0011 d26.2 010 11010 010110 0101 010110 0101 d26.3 011 11010 010110 1100 010110 0011 d27.2 010 11011 110110 0101 001001 0101 d27.3 011 11011 110110 0011 001001 1100 d28.2 010 11100 001110 0101 001110 0101 d28.3 011 11100 001110 1100 001110 0011 d29.2 010 11101 101110 0101 010001 0101 d29.3 011 11101 101110 0011 010001 1100 d30.2 010 11110 011110 0101 100001 0101 d30.3 011 11110 011110 0011 100001 1100 d31.2 010 11111 101011 0101 010100 0101 d31.3 011 11111 101011 0011 010100 1100 table 15. valid data characters (txctx[0] = 0, rxstx[2:0] = 000) (continued) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 39 of 43 d0.4 100 00000 100111 0010 011000 1101 d0.5 101 00000 100111 1010 011000 1010 d1.4 100 00001 011101 0010 100010 1101 d1.5 101 00001 011101 1010 100010 1010 d2.4 100 00010 101101 0010 010010 1101 d2.5 101 00010 101101 1010 010010 1010 d3.4 100 00011 110001 1101 110001 0010 d3.5 101 00011 110001 1010 110001 1010 d4.4 100 00100 110101 0010 001010 1101 d4.5 101 00100 110101 1010 001010 1010 d5.4 100 00101 101001 1101 101001 0010 d5.5 101 00101 101001 1010 101001 1010 d6.4 100 00110 011001 1101 011001 0010 d6.5 101 00110 011001 1010 011001 1010 d7.4 100 00111 111000 1101 000111 0010 d7.5 101 00111 111000 1010 000111 1010 d8.4 100 01000 111001 0010 000110 1101 d8.5 101 01000 111001 1010 000110 1010 d9.4 100 01001 100101 1101 100101 0010 d9.5 101 01001 100101 1010 100101 1010 d10.4 100 01010 010101 1101 010101 0010 d10.5 101 01010 010101 1010 010101 1010 d11.4 100 01011 110100 1101 110100 0010 d11.5 101 01011 110100 1010 110100 1010 d12.4 100 01100 001101 1101 001101 0010 d12.5 101 01100 001101 1010 001101 1010 d13.4 100 01101 101100 1101 101100 0010 d13.5 101 01101 101100 1010 101100 1010 d14.4 100 01110 011100 1101 011100 0010 d14.5 101 01110 011100 1010 011100 1010 d15.4 100 01111 010111 0010 101000 1101 d15.5 101 01111 010111 1010 101000 1010 d16.4 100 10000 011011 0010 100100 1101 d16.5 101 10000 011011 1010 100100 1010 d17.4 100 10001 100011 1101 100011 0010 d17.5 101 10001 100011 1010 100011 1010 d18.4 100 10010 010011 1101 010011 0010 d18.5 101 10010 010011 1010 010011 1010 d19.4 100 10011 110010 1101 110010 0010 d19.5 101 10011 110010 1010 110010 1010 d20.4 100 10100 001011 1101 001011 0010 d20.5 101 10100 001011 1010 001011 1010 d21.4 100 10101 101010 1101 101010 0010 d21.5 101 10101 101010 1010 101010 1010 d22.4 100 10110 011010 1101 011010 0010 d22.5 101 10110 011010 1010 011010 1010 d23.4 100 10111 111010 0010 000101 1101 d23.5 101 10111 111010 1010 000101 1010 d24.4 100 11000 110011 0010 001100 1101 d24.5 101 11000 110011 1010 001100 1010 d25.4 100 11001 100110 1101 100110 0010 d25.5 101 11001 100110 1010 100110 1010 d26.4 100 11010 010110 1101 010110 0010 d26.5 101 11010 010110 1010 010110 1010 d27.4 100 11011 110110 0010 001001 1101 d27.5 101 11011 110110 1010 001001 1010 d28.4 100 11100 001110 1101 001110 0010 d28.5 101 11100 001110 1010 001110 1010 d29.4 100 11101 101110 0010 010001 1101 d29.5 101 11101 101110 1010 010001 1010 d30.4 100 11110 011110 0010 100001 1101 d30.5 101 11110 011110 1010 100001 1010 d31.4 100 11111 101011 0010 010100 1101 d31.5 101 11111 101011 1010 010100 1010 table 15. valid data characters (txctx[0] = 0, rxstx[2:0] = 000) (continued) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 40 of 43 d0.6 110 00000 100111 0110 011000 0110 d0.7 111 00000 100111 0001 011000 1110 d1.6 110 00001 011101 0110 100010 0110 d1.7 111 00001 011101 0001 100010 1110 d2.6 110 00010 101101 0110 010010 0110 d2.7 111 00010 101101 0001 010010 1110 d3.6 110 00011 110001 0110 110001 0110 d3.7 111 00011 110001 1110 110001 0001 d4.6 110 00100 110101 0110 001010 0110 d4.7 111 00100 110101 0001 001010 1110 d5.6 110 00101 101001 0110 101001 0110 d5.7 111 00101 101001 1110 101001 0001 d6.6 110 00110 011001 0110 011001 0110 d6.7 111 00110 011001 1110 011001 0001 d7.6 110 00111 111000 0110 000111 0110 d7.7 111 00111 111000 1110 000111 0001 d8.6 110 01000 111001 0110 000110 0110 d8.7 111 01000 111001 0001 000110 1110 d9.6 110 01001 100101 0110 100101 0110 d9.7 111 01001 100101 1110 100101 0001 d10.6 110 01010 010101 0110 010101 0110 d10.7 111 01010 010101 1110 010101 0001 d11.6 110 01011 110100 0110 110100 0110 d11.7 111 01011 110100 1110 110100 1000 d12.6 110 01100 001101 0110 001101 0110 d12.7 111 01100 001101 1110 001101 0001 d13.6 110 01101 101100 0110 101100 0110 d13.7 111 01101 101100 1110 101100 1000 d14.6 110 01110 011100 0110 011100 0110 d14.7 111 01110 011100 1110 011100 1000 d15.6 110 01111 010111 0110 101000 0110 d15.7 111 01111 010111 0001 101000 1110 d16.6 110 10000 011011 0110 100100 0110 d16.7 111 10000 011011 0001 100100 1110 d17.6 110 10001 100011 0110 100011 0110 d17.7 111 10001 100011 0111 100011 0001 d18.6 110 10010 010011 0110 010011 0110 d18.7 111 10010 010011 0111 010011 0001 d19.6 110 10011 110010 0110 110010 0110 d19.7 111 10011 110010 1110 110010 0001 d20.6 110 10100 001011 0110 001011 0110 d20.7 111 10100 001011 0111 001011 0001 d21.6 110 10101 101010 0110 101010 0110 d21.7 111 10101 101010 1110 101010 0001 d22.6 110 10110 011010 0110 011010 0110 d22.7 111 10110 011010 1110 011010 0001 d23.6 110 10111 111010 0110 000101 0110 d23.7 111 10111 111010 0001 000101 1110 d24.6 110 11000 110011 0110 001100 0110 d24.7 111 11000 110011 0001 001100 1110 d25.6 110 11001 100110 0110 100110 0110 d25.7 111 11001 100110 1110 100110 0001 d26.6 110 11010 010110 0110 010110 0110 d26.7 111 11010 010110 1110 010110 0001 d27.6 110 11011 110110 0110 001001 0110 d27.7 111 11011 110110 0001 001001 1110 d28.6 110 11100 001110 0110 001110 0110 d28.7 111 11100 001110 1110 001110 0001 d29.6 110 11101 101110 0110 010001 0110 d29.7 111 11101 101110 0001 010001 1110 d30.6 110 11110 011110 0110 100001 0110 d30.7 111 11110 011110 0001 100001 1110 d31.6 110 11111 101011 0110 010100 0110 d31.7 111 11111 101011 0001 010100 1110 table 15. valid data characters (txctx[0] = 0, rxstx[2:0] = 000) (continued) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 41 of 43 table 16. valid special character codes and sequences (txctx = special character code or rxstx[2:0] = 001) [40, 41] s.c. code name s.c. byte name current rd ? abcdei fghj current rd+ abcdei fghj cypress alternate s.c. byte name [42] bits hgf edcba s.c. byte name [42] bits hgf edcba k28.0 c0.0 (c00) 000 00000 c28.0 (c1c) 000 11100 001111 0100 110000 1011 k28.1 [43] c1.0 (c01) 000 00001 c28.1 (c3c) 001 11100 001111 1001 110000 0110 k28.2 [43] c2.0 (c02) 000 00010 c28.2 (c5c) 010 11100 001111 0101 110000 1010 k28.3 c3.0 (c03) 000 00011 c28.3 (c7c) 011 11100 001111 0011 110000 1100 k28.4 [43] c4.0 (c04) 000 00100 c28.4 (c9c) 100 11100 001111 0010 110000 1101 k28.5 [43, 44] c5.0 (c05) 000 00101 c28.5 (cbc) 101 11100 001111 1010 110000 0101 k28.6 [43] c6.0 (c06) 000 00110 c28.6 (cdc) 110 11100 001111 0110 110000 1001 k28.7 [43, 45] c7.0 (c07) 000 00111 c28.7 (cfc) 111 11100 001111 1000 110000 0111 k23.7 c8.0 (c08) 000 01000 c23.7 (cf7) 111 10111 111010 1000 000101 0111 k27.7 c9.0 (c09) 000 01001 c27.7 (cfb) 111 11011 110110 1000 001001 0111 k29.7 c10.0 (c0a) 000 01010 c29.7 (cfd) 111 11101 101110 1000 010001 0111 k30.7 c11.0 (c0b) 000 01011 c30.7 (cfe) 111 11110 011110 1000 100001 0111 end of frame sequence eofxx c2.1 (c22) 001 00010 c2.1 (c22) 001 00010 ? k28.5,dn.xxx0 [46] +k28.5,dn.xxx1 [46] code rule violatio n and svs tx pattern exception [45, 47] c0.7 (ce0) 111 00000 c0.7 (ce0) 111 00000 100111 1000 011000 0111 ? k28.5 [48] c1.7 (ce1) 111 00001 c1.7 (ce1) 111 00001 001111 1010 001111 1010 +k28.5 [49] c2.7 (ce2) 111 00010 c2.7 (ce2) 111 00010 110000 0101 110000 0101 running disparity violation pattern exception [50] c4.7 (ce4) 111 00100 c4.7 (ce4) 111 00100 110111 0101 001000 1010 notes: 40. all codes not shown are reserved. 41. notation for special character code name is consistent with fibre channel and escon naming conv entions. special character co de name is intended to describe binary information present on i/o pins. common usage for t he name can either be in the form used for describing data p atterns (i.e., c0.0 through c31.7), or in hex notation (i.e., cnn where nn = the specified value between 00 and ff). 42. both the cypress and alternate encodings may be used for data transmission to generate specific special character codes. the decoding process for received characters generates cypress codes or alternate codes as selected by the boe[7:0] configuration inputs. 43. these characters are used for control of escon interfaces. they can be sent as embedded commands or other markers when not o perating using escon protocols. 44. the k28.5 character is used for framing o perations by the receiver. it is also t he pad or fill character transmitted to main tain the serial link when no user data is available. 45. care must be taken when using this special character code. when a c7.0 or a c0.7 is followed by a d11.x or d20.x, an alias k 28.5 sync character is created. these sequences can cause erroneous frami ng and should be avoided while rfenx = 1. 46. c2.1 = transmit either ?k28.5+ or +k28.5? as determined by current rd and modify the transmission character that follows, by setting its least significant bit to 1 or 0. if current rd at the start of the following character is plus (+) the lsb is set to 0, and if current rd is minus (? ) the lsb becomes 1. this modification allows construction of x3.230 ?eof? frame delimiters wherein the second data byte is determined by the current rd. for example, to send ?eofdt? the controller could issue the s equence c2.1?d21.4? d21.4?d21.4, and the hotlink transmitter sends either k28.5?d21.4?d21.4?d21.4 or k28.5?d21.5? d21.4?d21.4 based on current rd. likewise to send ?eofdti? the controller could issue t he sequence c2.1?d10.4?d21.4?d21.4, and the hotlink transmitter sends either k28.5?d10.4?d21.4? d21.4 or k28.5?d10.5?d21.4?d21.4 based on c urrent rd. the receiver never outputs this special character, since k28.5 is decoded as c5.0, c1.7, or c2.7, and the subsequent bytes are decoded as data. 47. c0.7 = transmit a deliberate code rule violation. the code c hosen for this function follows the normal running disparity rul es. transmission of this special character has the same effect as asserting txsvs = high. the re ceiver only outputs this special character if the transmission c haracter being decoded is not found in the tables. 48. c1.7 = transmit negative k28.5 ( ? k28.5+) disregarding current rd. the receiver only outputs this special character if k28.5 is received with the wrong running disparity. the receiver outputs c1.7 if ? k28.5 is received with rd+, otherwise k28.5 is decoded as c5.0 or c2.7. 49. c2.7 = transmit positive k28.5 (+k28.5 ? ) disregarding current rd. the receiver only outputs this spec ial character if k28.5 is received with the wrong running disparity. the receiver outputs c2.7 if +k28.5 is received with rd ? , otherwise k28.5 is decoded as c5.0 or c1.7. 50. c4.7 = transmit a deliberate code rule violation to indicate a running disparity violation. the receiver only outputs this s pecial character if the transmission character being decoded is found in the tabl es, but running disparity does not match. th is might indicate that an error occurre d in a prior byte.
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 42 of 43 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram hotlink is a registered trademark and hotl ink ii and multiframe are trademarks of cy press semiconductor. cpri is a trademark of siemens ag. ibm and escon are register ed trademarks, and ficon is a trademark, of international business machines. all product and company names mention ed in this document may be the trademarks of their respective holders. ordering information speed ordering code package name package type operating range standard cyp15g0403dxb-bgc bl256 256-ball thermally enhanced ball grid array commercial standard cyp15g0403dxb-bgi bl256 256-ball thermally enhanced ball grid array industrial standard CYV15G0403DXB-bgc bl256 256-ball thermally enhanced ball grid array commercial standard CYV15G0403DXB-bgi bl256 256-ball thermally enhanced ball grid array industrial obsai cyw15g0403dxb-bgc bl256 256-ball thermally enhanced ball grid array commercial obsai cyw15g0403dxb-bgi bl256 256-ball thermally enhanced ball grid array industrial standard cyp15g0403dxb-bgxc bl256 pb-free 256-ball thermally enhanced ball grid array commercial standard cyp15g0403dxb-bgxi bl256 pb-free 256-ball thermally enhanced ball grid array industrial standard CYV15G0403DXB-bgxc bl256 pb-free 256-ball thermally enhanced ball grid array commercial standard CYV15G0403DXB-bgxi bl256 pb-free 256-ball thermally enhanced ball grid array industrial obsai cyw15g0403dxb-bgxc bl256 pb-free 256-ball thermally enhanced ball grid array commercial obsai cyw15g0403dxb-bgxi bl256 pb-free 256-ball thermally enhanced ball grid array industrial 256-lead l2 ball grid array (27 x 27 x 1.57 mm) bl256 51-85123-*e
cyv15g0403dx b cyw15g0403dxb cyp15g0403dxb document #: 38-02065 rev. *e page 43 of 43 document history page document title: cyp(v)(w)15g0403dxb independent clock quad hotlink ii? transceiver document number: 38-02065 rev. ecn no. issue date orig. of change description of change ** 118422 09/24/02 lnm new data sheet *a 125289 04/04/03 cgx revised entire data sheet redefined device *b 128692 08/14/03 pds provided ac timing information for txerrx added additional information regarding the availability of half-rate rxclkx when refclkx is a full-rate clock with rxckselx = 1 added influence of ulcx input on lfix status added influence of decmodex on decoder bypass revised the text for ?device config uration and control interface? for better clarity removed the timing parameter t rrefdv and added the timing parameter t rrefdw instead. this change was done to provide a more meaningful timing parameter revised t rrefda from 9.5 ns to 9.7 ns added additional information to ?device configuration strategy? *c 234390 see ecn pds removed dependence of decmodex on decoder bypass. revised ac timing parameters (ac electrical characteristics) to match final device characterization. expanded the cdr range controller?s permissible frequency offset between incoming serial signalling rate and reference clock from 200-ppm to 1500-ppm (changed parameter t refrx ). *d 338721 see ecn sua added cyw15g0403dxb part number for obsai rp3 compliance to support operating data rate up to 1540 mbaud. made changes to reflect obsai rp3 and cpr compliance. added pb-free package option for all parts listed in the datasheet. modified timing parameters changed mbd to mbaud in spdsel pin description *e 384307 see ecn agt revised setup and hold time parameters (t txdh , t trefds , t trefdh , t rxdv? , t rxdv+ , t rxdv+ , t refxdv? , t refxdv+ )

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